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19.4 Interrupt of UART
The UART has the reception and transmission interrupts.
The interrupt of the UART can activate the DMA transfer and extended intelligent I/O
2
service (EI
OS).
■
Interrupt of UART
The following table shows the interrupt control bit and interrupt source of the UART.
Interrupt request flag
Interrupt request output
enable bit
Interrupt generation
source
■
Interrupt source related to UART
The interrupts occurs at receiving and transmitting UART.
The interrupt request occurs with the sources as shown below.
•
When the reception data is loaded to the serial input register (SIDR)
•
When the reception error (parity, overrun, framing error) occurs
•
When the transmission data is transferred from the serial output register (SODR) to the
transmission shift register
UART reception interrupt
Data reception completion SSR:
RDRF (bit12)
Framing error SSR:FRE (bit13)
Overrun error SSR:ORE (bit14)
Parity error SSR:PE (bit15)
SSR:RIE (bit9)
At receiving UART
CHAPTER 19 UART
UART transmission interrupt
SSR:TDRE (bit11)
SSR:TIE (bit8)
At transmitting UART
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