Overview Of Clocks - Fujitsu MB90480 Series Hardware Manual

CHAPTER 5 CLOCKS
5.1

Overview of Clocks

The clock generator controls the operations of internal clocks, which are the operation
clocks of the CPU and peripheral functions. In this document, the clocks are called as
follows according to clock type:
• Machine clock: Defined as an internal clock.
• Machine cycle: Defined as one period of a machine clock.
• Oscillation clock: Defined as a clock supplied via a high-speed oscillation pin.
• PLL clock: Defined as a clock using internal PLL oscillation.
• Sub-clock: Clock divided by four, provided from a low-speed oscillation pin.
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Overview of clocks
The clock generator contains an oscillation circuit and generates an oscillation clock and sub-
clock by using an external connection to an oscillator. The generator generates an oscillation
clock by inputting a clock generated externally. The generator contains a PLL clock multiplier
circuit and generates four multiplication clocks of an oscillation clock. The clock generator
controls the oscillation stabilization wait time, PLL clock multiplication, and operations of internal
clocks by changing the clock of the clock selector.
❍ Oscillation clock (HCLK)
This clock is generated by connecting an oscillator to the high-speed oscillation pin or by
inputting an external clock.
❍ Sub-clock (SCLK)
This clock operates the watch timer. It can also be used as a low-speed machine clock.
This clock is divided by four and created by connecting an oscillator to the low-speed oscillation
pin or by inputting an external clock.
❍ Main clock (MCLK)
This is a clock of the oscillation clock divided by two, and is used as an input clock to the
timebase timer and clock selector.
❍ PLL clock (PCLK)
This clock is a clock obtained by multiplying with built-in PLL clock multiplier circuit (PLL
oscillation circuit). Four types of the clocks can be selected.
❍ Machine clock (φ)
This clock is an operation clock of the CPU and peripheral functions. One period of this clock is
used as a machine cycle (1/φ). One clock can be selected from among the main clock (clock of
oscillation clock divided by two), sub-clock, and four types of multiplication clocks.
Note:
Oscillation clocks have an oscillation frequency ranging from 4.5 to 25 MHz. At using PLL, a
machine clock from 20 to 25 MHz is used, set the PLL2 bit of the PLLOS register to 1. The
maximum operating frequency of the CPU and peripheral functions is 25 MHz. If a multiply-by rate
exceeding the maximum operating frequency is specified, the device will not operate correctly.
PLL oscillation can be between 4.5 and 25 MHz. This oscillation range varies depending on
operating voltage and the multiplication rate.
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