Table of Contents
Advertisement
6.4
CPU Intermittent Operation Mode
The CPU intermittent operation mode reduces power consumption by intermittently
operating the CPU while operating external buses and peripheral functions at high
speeds.
■
CPU intermittent operation mode
To delay activation of the internal bus cycle, the CPU intermittent operation mode stops clocks
supplied to the CPU for a preset period for each instruction during access to registers,
embedded memory (ROM or RAM), I/O, peripheral functions, and external buses. Low-power
consumption processing is possible by lowering the CPU execution speed while high-speed
peripheral clocks are supplied to peripheral functions.
•
Select the number of clock pause cycles supplied to the CPU using a bit for selecting the
number of CPU-clock pause cycles (CG1 or CG0) of the low-power consumption mode
control register (LPMCR).
•
Use the same clock as that for the peripheral functions when operating external buses.
•
The instruction execution time when the CPU intermittent operation mode is set can be
calculated by dividing the number of instruction executions for accessing registers,
embedded memory, embedded peripheral functions, and external buses by the number of
pauses cycles. The correction value thus obtained is added to the usual execution time.
Figure 6.4-1 illustrates operation clocks in the CPU intermittent operation mode.
Peripheral clock
CPU clock
Figure 6.4-1 Clocks in CPU intermittent operation mode
CHAPTER 6 LOW-POWER CONSUMPTION MODE
One
instruction
Pause cycle
execution
cycle
Internal bus activation
131
Advertisement
Table of Contents
