Flow Of Hardware Interrupt Operation - Fujitsu MB90480 Series Hardware Manual

CHAPTER 3 INTERRUPT
3.4.2

Flow of Hardware Interrupt Operation

If an interrupt request is generated by a peripheral function, the interrupt controller
transfers its interrupt level to the CPU. If the CPU accepts the interrupt request, the
instruction currently being executed is temporarily suspended to execute the interrupt
processing routine or to start μDMAC. If a software interrupt is generated by the INT
instruction, the interrupt processing routine is executed regardless of the CPU state.
Moreover, if a software interrupt is generated by the INT instruction, the hardware
interrupt is prohibited.
■
Hardware interrupt operation flow
Figure 3.4-3 shows the hardware interrupt operation flow.
String-type
instruction being
executed*
*
I
IF
IE
ILM : Interrupt level mask register (in PS)
58
Figure 3.4-3 Flow of hardware interrupt operation
START
Main program
I&IF&IE=1
YES
AND
ILM>IL
NO
Reading and decoding
of next instruction
YES
INT instruction?
NO
YES
RETI instruction?
NO
Execution of normal instruction
(Including interrupt processing)
Completed
NO
reiteration of string-type
instruction*
YES
Moving of pointer to next
instruction if PC updated
: When a string-type instruction is being executed, the
interrupt condition is determined in each step.
: Interrupt permission flag of condition code register
(CCR)
: Interrupt request flag of peripheral function
: Interrupt permission flag of peripheral function
Software
interrupt and
exception
processing
Hardware
interrupt
Saving dedicated registers
in the system stack
Saving dedicated registers
in the system stack
I 0
Hardware interrupt
prohibited
(If an interrupt request is
accepted, its interrupt
level is transferred to ILM.)
Execution of
interrupt return
(Enabling system stack)
Return of dedicated registers
from system stack and then
its return to routine that
existed before calling of
PCB, PC
interrupt routine
(Branching to interrupt
processing routine)
ENX : Request flag executing DMA of DMA enable register
(DER)
IL : Interrupt level setting bit in interrupt control register
(ICR)
S : Stack flag in condition code register (CCR)
PCB : Program counter bank register
PC : Program counter*
Interrupt start and return processing
μDMAC
YES
ENX=1?
μDMAC processing
NO
Has the
specified number of
YES
times been completed?
Or did a peripheral function
issue a complete
request?
NO
ILM IL
S 1
Interrupt vector