Memory Sequence - Fujitsu PRIMERGY CX2560 M4 Upgrade And Maintenance Manual

7.1.1

Memory sequence

– Populate memory slot 1 / channel A (DIMM-1A) first.
– Within the 6 channels, memory slot 1 must be populated prior to slot 2.
– If memory modules with different capacities are used:
– Install modules with higher capacities first.
– Within a channel, install modules in descending order of capacity.
– If memory modules with different speeds are used, the lowest clock rate
applies for all DIMMs.
Minimum configuration
Minimum configuration is 2x CPU and 2x memory.
Maximum configurations
– up to 3TB using LRDIMM
– up to 6TB using AEP
First Memory (one module) has to be selected for an orderable basic unit per
CPU.
– Memory upgrade is possible by 1x memory units.
– SDDC (Chipkill) is supported for memory modules.
CX2550/60/70 M4
Upgrade and Maintenance Manual
Main memory
185