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TLC0820ACDW (TI)FLAT PACKAGE
TLC0820ACDWR
C-MOS 8-BIT SEMIFLASH TYPE A/D CONVERTER
ANLG
IN
1
V
20
DD
D0
OUT
2
NC
19
(LSB)
OFLW
D1
3
18
OUT
OUT
D7
D2
4
17
OUT
OUT
(MSB)
D3
OUT
5
16
D6
OUT
WR
/RDY
6
15
IN/OUT
D5
OUT
MODE
7
14
IN
D4
OUT
RD
CS
IN
8
13
IN
INT
OUT
9
12
REF+
IN
10
11
GND
REF_
IN
INPUT
OUTPUT
ANLG
: ANALOG SIGNAL
D0 - D7
CS
INT
: CHIP SELECT
OFLW
MODE
: MODE
RD
: READ
REF+, REF_
: REFERENCE VOLTAGE +, _
INPUT/OUTPUT
WR
/RDY
12
REF +
4-BIT FLASH
4
11
A/D CONVERTER
REF _
1
(HIGHER)
ANLG
4-BIT
D/A CONVERTER
4-BIT FLASH
A/D CONVERTER
_1
(LOWER)
+1
7
MODE
13
CS
8
RD
6
WR/RDY
UPD4702G (NEC)
C-MOS INCREMENTAL ENCODER 8-BIT UPDOWN COUNTER
—TOP VIEW—
RESET
1
V
20
DD
CARRY
A
2
19
2
3
BORROW
B
3
18
STB
4
17
NC
OE
CD0
5
16
16
17
CD1
6
15
CD7
1
CD2
7
14
CD6
A
B
CD3
8
13
CD5
BORROW
CARRY
9
12
CD4
NC
CD0 - 7
OE
10
11
GND
NC
RESET
STB
1
RESET
2
A
PHASE
DISCRIMINATION
3
EDGE DETECTOR
B
16
OE
17
STB
BKP-5090
12
2
REF+
(LSB)D0
11
3
REF_
D1
4
D2
1
5
ANLG
D3
14
D4
15
D5
16
D6
17
(MSB)D7
7
MODE
13
18
CS
OFLW
8
RD
6
9
WR
/RDY
INT
: DIGITAL SIGNAL
: INTERRUPT
: OVERFLOW
: L : WRITE/H : READY
2
D0(LSB)
4
3
D1
4
D2
5
D3
OUTPUT
14
D4
LATCH
4
15
AND
D5
16
3-STATE
D6
BUFFER
17
D7(MSB)
4
18
OFLW
TIMING
9
&
INT
CONTROL
5
CD0
6
CD1
7
CD2
8
CD3
A
12
CD4
B
13
CD5
14
CD6
15
CD7
18
BORROW
OE
19
CARRY
STB
RESET
: INCREMENTAL SIGNAL (PHASE A) INPUT
: INCREMENTAL SIGNAL (PHASE B) INPUT
: BORROW PULSE OUTPUT
: CARRY PULSE OUTPUT
: COUNT DATA OUTPUT
: OUTPUT CONTROL SIGNAL INPUT
: COUNTER RESET INPUT
: LATCH STROBE SIGNAL INPUT
19
CARRY
8-BIT
UP/DOWN COUNTER
18
BORROW
8-BIT LATCH
TRI-STATE OUTPUT
5-8
12-15
CD0 - CD7
UPD71055GB-10-3B4 (NEC)
C-MOS PARALLEL INTERFACE UNIT
—TOP VIEW—
44 43 42 41 40 39 38 37 36 35 34
NC
INDEX
NC
NC
1
CS
2
3
4
A1
GND
5
A0
6
P27
7
P26
8
P25
9
P24
10
P20
11
V
P21
DD
12 13 14 15 16 17 18 19 20 21 22
A1, A0
; ADDRESS
P17 - P10
CS
; CHIP SELECT
P27 - P20
RD
D7 - D0
; DATA BUS
WR
P07 - P00
; PORT 0
IC
; INTERNALLY CONNECTED
CS
RD
WR
A1
A0
OPERATION
PORT0 → DATA • BUS
0
0
1
0
0
PORT1 → DATA • BUS
0
0
1
0
1
PORT2 → DATA • BUS
0
0
1
1
0
0
0
1
1
1
0
0
0
X
X
DATA • BUS → PORT0
0
1
0
0
0
DATA • BUS → PORT1
0
1
0
0
1
DATA • BUS → PORT2
0
1
0
1
0
DATA • BUS → COMMAND REGISTER
0
1
0
1
1
0
1
1
X
X
HIGH IMPEDANCE
1
X
X
X
X
8
24 - 31
DATA BUS
D7 - D0
BUFF
GROUP
CONTROL
44
RD
35
WR
READ/
4
COMMAND
WRITE
A1
5
REGISTER
CONTROL
A0
32
RESET
2
CS
GROUP
CONTROL
TL084CPW-E05
TL084CPW-E20 (TI)FLAT PACKAGE
OPERATIONAL AMPLIFIER
(J FET INPUT)
—TOP VIEW—
14
13
12
11
10
9
8
V
EE
_
_
_
_
V
CC
1
2
3
4
5
6
7
P00
P01
P02
33
2
P03
CS
RESET
32
P04
5
31
A0
P05
D0
4
A1
P06
30
D1
P07
29
D2
35
P10
WR
28
D3
44
P11
RD
27
D4
P12
24
26
D5
D7
P13
25
D6
P14
25
D6
26
D5
P15
D7
24
27
D4
P16
23
28
D3
P17
29
D2
P20
30
D1
P21
31
D0
P22
P23
32
RESET
P24
; PORT 1
P25
; PORT 2
P26
; READ STROBE
P27
; WRITE STROBE
CPU ACTION
INPUT
INPUT
INPUT
DISABLE
OUTPUT
OUTPUT
OUTPUT
OUTPUT
0
: LOW LEVEL
1
: HIGH LEVEL
X
: DON'T CARE
8
36 - 43
P07 - P00
PORT 0
6 - 9
P27 - P24
8
PORT 2
13 - 10
P23 - P20
22 - 18,
16 - 14
8
P17 - P10
PORT 1
6-17
IC
43
42
41
40
39
38
37
36
14
15
16
18
19
20
21
22
10
11
12
13
9
8
7
6
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