Hitachi SH7751 Hardware Manual page 521

Bits 14 to 10—Reserved: These bits are always read as 0, and should only be written with 0.
Bits 9 and 8—Priority Mode 1 and 0 (PR1, PR0): These bits determine the order of priority for
channel execution when transfer requests are made for a number of channels simultaneously.
Bit 9: PR1 Bit 8: PR0
0 0
1
1 0
1
Bits 7 to 3—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 2—Address Error Flag (AE): Indicates that an address error has occurred during DMA
transfer. If this bit is set during data transfer, transfers on all channels are suspended, and an
interrupt request (DMAE) is generated. The CPU cannot write 1 to AE. This bit can only be
cleared by writing 0 after reading 1.
Bit 2: AE
0
1
Bit 1—NMI Flag (NMIF): Indicates that NMI has been input. This bit is set regardless of
whether or not the DMAC is operating. If this bit is set during data transfer, transfers on all
channels are suspended. The CPU cannot write 1 to NMIF. This bit can only be cleared by writing
0 after reading 1.
Bit 1: NMIF
0
1
Rev. 3.0, 04/02, page 482 of 1064
Description
CH0 > CH1 > CH2 > CH3
CH0 > CH2 > CH3 > CH1
CH2 > CH0 > CH1 > CH3
Round robin mode
Description
No address error, DMA transfer enabled
[Clearing condition]
When 0 is written to AE after reading AE = 1
Address error, DMA transfer disabled
[Setting condition]
When an address error is caused by the DMAC
Description
No NMI input, DMA transfer enabled
[Clearing condition]
When 0 is written to NMIF after reading NMIF = 1
NMI input, DMA transfer disabled
[Setting condition]
When an NMI interrupt is generated
(Initial value)
(Initial value)
(Initial value)