Table 7.8 System Control Instructions - Hitachi SH7751 Hardware Manual

Table 7.8 System Control Instructions
Instruction
CLRMAC
CLRS
CLRT
LDC Rm,SR
LDC Rm,GBR
LDC Rm,VBR
LDC Rm,SSR
LDC Rm,SPC
LDC Rm,DBR
LDC Rm,Rn_BANK
LDC.L @Rm+,SR
LDC.L @Rm+,GBR
LDC.L @Rm+,VBR
LDC.L @Rm+,SSR
LDC.L @Rm+,SPC
LDC.L @Rm+,DBR
LDC.L @Rm+,Rn_BANK
LDS Rm,MACH
LDS Rm,MACL
LDS Rm,PR
LDS.L @Rm+,MACH
LDS.L @Rm+,MACL
LDS.L @Rm+,PR
LDTLB
MOVCA.L R0,@Rn
NOP
OCBI @Rn
OCBP @Rn
OCBWB @Rn
PREF @Rn
RTE
Operation

0 MACH, MACL

0 S

0 T

Rm SR

Rm GBR

Rm VBR

Rm SSR

Rm SPC

Rm DBR

Rm Rn_BANK (n = 0 to 7)
 
(Rm) SR, Rm + 4
 
(Rm) GBR, Rm + 4
 
(Rm) VBR, Rm + 4
 
(Rm) SSR, Rm + 4
 
(Rm) SPC, Rm + 4
 
(Rm) DBR, Rm + 4

(Rm) Rn_BANK,

Rm + 4 Rm

Rm MACH

Rm MACL

Rm PR

(Rm) MACH, Rm + 4

(Rm) MACL, Rm + 4
 
(Rm) PR, Rm + 4

PTEH/PTEL TLB

R0 (Rn) (without fetching
cache block)
No operation
Invalidates operand cache block 0000nnnn10010011 —
Writes back and invalidates
operand cache block
Writes back operand cache
block

(Rn) operand cache
Delayed branch, SSR/SPC
SR/PC
Instruction Code
0000000000101000 —
0000000001001000 —
0000000000001000 —
0100mmmm00001110 Privileged
0100mmmm00011110 —
0100mmmm00101110 Privileged
0100mmmm00111110 Privileged
0100mmmm01001110 Privileged
0100mmmm11111010 Privileged
0100mmmm1nnn1110 Privileged
Rm 0100mmmm00000111 Privileged
Rm 0100mmmm00010111 —
Rm 0100mmmm00100111 Privileged
Rm 0100mmmm00110111 Privileged
Rm 0100mmmm01000111 Privileged
Rm 0100mmmm11110110 Privileged
0100mmmm1nnn0111 Privileged
0100mmmm00001010 —
0100mmmm00011010 —
0100mmmm00101010 —

Rm 0100mmmm00000110 —

Rm 0100mmmm00010110 —
Rm 0100mmmm00100110 —
0000000000111000 Privileged
0000nnnn11000011 —
0000000000001001 —
0000nnnn10100011 —
0000nnnn10110011 —
0000nnnn10000011 —

0000000000101011 Privileged
Rev. 3.0, 04/02, page 181 of 1064
Privileged T Bit
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0
LSB
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LSB
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