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ATI:
Alarm interrupt
PRI:
Periodic interrupt
CUI:
Carry-up interrupt
ERI:
Receive-error interrupt
RXI:
Receive-data-full interrupt
TXI:
Transmit-data-empty interrupt
TEI:
Transmit-end interrupt
BRI:
Break interrupt request
ITI:
Interval timer interrupt
RCMI:
Compare-match interrupt
ROVI:
Refresh counter overflow interrupt
H-UDI: H-UDI interrupt
GPIOI: I/O port interrupt
DMTE0–DMTE7: DMAC transfer end interrupts
DMAE:
PCISERR:
PCIERR:
PCIPWDWN:
PCIPWON:
PCIDMA0 to 3:
19.3
Register Descriptions
19.3.1
Interrupt Priority Registers A to D (IPRA–IPRD)
Interrupt priority registers A to D (IPRA–IPRD) are 16-bit readable/writable registers that set
priority levels from 0 to 15 for on-chip peripheral module interrupts. IPRA to IPRC are initialized
to H'0000 and IPRD is to H'DA74 by a reset. They are not initialized in standby mode.
IPRA to IPRC
Bit:
15
Initial value:
0
R/W:
R/W
Bit:
7
Initial value:
0
R/W:
R/W
DMAC address error interrupt
PCIC SERR error interrupt
PCIC error interrupt
PCIC power-down request interrupt
PCIC power-ON request interrupt
PCIC DMA transfer end interrupts
14
13
0
0
R/W
R/W
6
5
0
0
R/W
R/W
12
11
0
0
R/W
R/W
4
3
0
0
R/W
R/W
Rev. 3.0, 04/02, page 739 of 1064
10
9
0
0
R/W
R/W
R/W
2
1
0
0
R/W
R/W
R/W
8
0
0
0
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