Hitachi SH7751 Hardware Manual page 36

Table 15.2 SCI Registers...................................................................................................... 572
Table 15.3 Examples of Bit Rates and SCBRR1 Settings in Asynchronous Mode ............. 591
Table 15.4 Examples of Bit Rates and SCBRR1 Settings in Synchronous Mode................ 594
Table 15.5 Maximum Bit Rate for Various Frequencies with Baud Rate Generator
(Asynchronous Mode)........................................................................................ 595
Table 15.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode).............. 596
Table 15.7 Maximum Bit Rate with External Clock Input (Synchronous Mode) ................ 596
Table 15.8 SCSMR1 Settings for Serial Transfer Format Selection .................................... 598
Table 15.9 SCSMR1 and SCSCR1 Settings for SCI Clock Source Selection...................... 598
Table 15.10 Serial Transfer Formats (Asynchronous Mode) ................................................. 600
Table 15.11 Receive Error Conditions ................................................................................... 608
Table 15.12 SCI Interrupt Sources ......................................................................................... 627
Table 15.13 SCSSR1 Status Flags and Transfer of Receive Data.......................................... 628
Table 16.1 SCIF Pins............................................................................................................ 636
Table 16.2 SCIF Registers.................................................................................................... 636
Table 16.3 SCSMR2 Settings for Serial Transfer Format Selection .................................... 663
Table 16.4 SCSCR2 Settings for SCIF Clock Source Selection .......................................... 664
Table 16.5 Serial Transfer Formats ...................................................................................... 665
Table 16.6 SCIF Interrupt Sources....................................................................................... 675
Table 17.1 Smart Card Interface Pins................................................................................... 681
Table 17.2 Smart Card Interface Registers........................................................................... 681
Table 17.3 Smart Card Interface Register Settings .............................................................. 689
Table 17.4 Values of n and Corresponding CKS1 and CKS0 Settings ................................ 691
Table 17.5 Examples of Bit Rate B (bits/s) for Various SCBRR1 Settings (When n = 0)... 692
Table 17.6 Examples of SCBRR1 Settings for Bit Rate B (bits/s) (When n = 0) ................ 692
Table 17.7 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) ........ 692
Table 17.8 Register Settings and SCK Pin State .................................................................. 693
Table 17.9 Smart Card Mode Operating States and Interrupt Sources................................. 700
Table 18.1 32-Bit General-Purpose I/O Port Pins ................................................................ 715
Table 18.2 SCI I/O Port Pins................................................................................................ 717
Table 18.3 SCIF I/O Port Pins.............................................................................................. 717
Table 18.4 I/O Port Registers ............................................................................................... 718
Table 19.1 INTC Pins........................................................................................................... 731
Table 19.2 INTC Registers................................................................................................... 731

Table 19.3 -
Table 19.4 Interrupt Exception Handling Sources and Priority Order ................................. 737
Table 19.5 Interrupt Request Sources and IPRA-IPRD Registers ....................................... 740
Table 19.6 Interrupt Request Sources and INTPRI00 Register............................................ 743
Table 19.7 Bit Allocation ..................................................................................................... 746
Table 19.8 Interrupt Response Time .................................................................................... 750
Table 20.1 UBC Registers.................................................................................................... 753
Table 21.1 H-UDI Pins......................................................................................................... 779
Table 21.2 H-UDI Registers................................................................................................. 780
 
Pins and Interrupt Levels................................................................ 734
Rev. 3.0, 04/02, page xxxv of xxxviii