Figure 3.3 Physical Address Space (Mmucr.at = 0) - Hitachi SH7751 Hardware Manual

H'0000 0000
H'8000 0000
H'A000 0000
Non-cacheable
H'C000 0000
H'E000 0000
Non-cacheable
H'FFFF FFFF
Privileged mode

Figure 3.3 Physical Address Space (MMUCR.AT = 0)

When performing access from the CPU to a PCMCIA interface area in the SH7751 Series, access
is always performed using the values of the SA and TC bits set in the PTEA register. Access to a
PCMCIA interface area by the DMAC is always performed using the DMAC's CHCRn.SSAn,
CHCRn.DSAn, CHCRn.STC, and CHCRn.DTC values. For details, see section 14, Direct
Memory Access Controller.
P0, P1, P3, U0 Areas: The P0, P1, P3, and U0 areas can be accessed using the cache. Whether or
not the cache is used is determined by the cache control register (CCR). When the cache is used,
with the exception of the P1 area, switching between the copy-back method and the write-through
method for write accesses is specified by the CCR.WT bit. For the P1 area, switching is specified
by the CCR.CB bit. Zeroizing the upper 3 bits of an address in these areas gives the corresponding
external memory space address. However, since area 7 in the external memory space is a reserved
area, a reserved area also appears in these areas.
P2 Area: The P2 area cannot be accessed using the cache. In the P2 area, zeroizing the upper 3
bits of an address gives the corresponding external memory space address. However, since area 7
in the external memory space is a reserved area, a reserved area also appears in this area.
P4 Area: The P4 area is mapped onto SH7751 Series on-chip I/O channels. This area cannot be
accessed using the cache. The P4 area is shown in detail in figure 3.4.
memory space
P0 area
Cacheable
P1 area
Cacheable
P2 area
P3 area
Cacheable
P4 area
External
Area 0
Area 1
Area 2
Area 3
Area 4
Cacheable
Area 5
Area 6
Area 7
Address error
Store queue area
Address error
User mode
Rev. 3.0, 04/02, page 59 of 1064
H'0000 0000
U0 area
H'8000 0000
H'E000 0000
H'E400 0000
H'FFFF FFFF