Register Configuration; Pin Configuration; Table 9.2 Power-Down Mode Registers; Table 9.3 Power-Down Mode Pins - Hitachi SH7751 Hardware Manual

9.1.2

Register Configuration

Table 9.2 shows the registers used for power-down mode control.
Table 9.2 Power-Down Mode Registers
Name Abbreviation
Standby control STBCR
register
Standby control STBCR2
register 2
Clock stop register CLKSTP00
Clock stop clear CLKSTPCLR00 W
register
9.1.3

Pin Configuration

Table 9.3 shows the pins used for power-down mode control.
Table 9.3 Power-Down Mode Pins
Pin Name
Processor status 1
Processor status 0
Sleep request
Hardware standby
request
Notes: H: High level
L: Low level
R/W
R/W
R/W
R/W
Abbreviation I/O
STATUS1 Output
STATUS0


Input
CA Input
Initial Value P4 Address
H'00 H'FFC00004 H'1FC00004
H'00 H'FFC00010 H'1FC00010
H'00000000 H'FE0A0000 H'1E0A0000
H'00000000 H'FE0A0008 H'1E0A0008
Function
Indicate the processor's operating status
(STATUS1, STATUS0).
HH: Reset
HL: Sleep mode
LH: Standby mode
LL: Normal operation
A transition to sleep mode is effected by
inputting a low-level to the pin.
A transition to hardware standby mode is
effected by inputting a low-level to the
pin.
Rev. 3.0, 04/02, page 217 of 1064
Area 7 Access
Address Size
8
8
32
32