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For a 32-bit bus:
17
16
15
Address
0
0
LMODE: RAS-CAS latency
BL:
Burst length
WT:
Wrap type (0: Sequential)
BL
LMODE
000: Reserved
000: Reserved
001: Reserved
001: 1
010: 4
010: 2
011: 8*
011: 3
100: Reserved
100: Reserved
101: Reserved
101: Reserved
110: Reserved
110: Reserved
111: Reserved
111: Reserved
Note: * SH7751R only
13.2.11 Refresh Timer Control/Status Register (RTCSR)
The refresh timer control/status register (RTCSR) is a 16-bit readable/writable register that
specifies the refresh cycle and whether interrupts are to be generated.
RTSCR is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or in
standby mode.
Bit:
15
—
Initial value:
0
R/W:
—
Bit:
7
CMF
Initial value:
0
R/W:
R/W
Rev. 3.0, 04/02, page 354 of 1064
14
13
12
11
0
0
0
0
0
14
13
—
—
0
0
—
—
6
5
CMIE
CKS2
0
0
R/W
R/W
10
9
8
7
6
0
0
LMO
LMO
LMO
DE2
DE1
DE0
10 bits set in case of 32-bit bus width
12
11
—
—
0
0
—
—
4
3
CKS1
CKS0
0
0
R/W
R/W
5
4
3
2
1
WT BL2 BL1 BL0
10
9
—
—
0
0
—
—
2
1
OVF
OVIE
LMTS
0
0
R/W
R/W
0
8
—
0
—
0
0
R/W
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