Pci Command Data Register At Error (Pciclr) - Hitachi SH7751 Hardware Manual

22.2.23 PCI Command Data Register at Error (PCICLR)

Bit: 31
MSTPIO MSTDMA0 MSTDMA1 MSTDMA2 MSTDMA3
Initial value: 0
PCI-R/W: R
PP Bus-R/W: R
Bit: 23
—
Initial value: 0
PCI-R/W: R
PP Bus-R/W: R
Bit: 15
—
Initial value: 0
PCI-R/W: R
PP Bus-R/W: R
Bit: 7
—
Initial value: 0
PCI-R/W: R
PP Bus-R/W: R
The PCI command data register at error (PCICLR) stores the type of transfer (MSTPIO,
MSTDMA0, MSTDMA1, MSTDMA2, MSTDMA3, or TGT) when an error occurs on the PCI
bus, and the PCI command (CMDLOG [3:0]). It is a 32-bit register that can be read from both the
PP bus and PCI bus.
Although bits 31 to 26 of the PCICLR register are initialized at a power-on reset and a software
reset, bits 3 through 0 are not initialized. When an error is detected, 1 is set in one of bits 31 to 26,
and the relevant command value is retained in bits 3 to 0.
A valid value is retained only when one of the PCIINT register bits is set to 1.
The error source holding circuit can only store one error source. For this reason, any second or
subsequent error factors are not stored if errors occur consecutively.
30 29 28
0 0
R R
R R
22 21 20
— —
0 0
R R
R R
14 13 12
— —
0 0
R R
R R
6 5
— —
0 0
R R
R R
27 26
TGT
0 0
R R
R R
19 18
— —
0 0
R R
R R
11 10
— —
0 0
R R
R R
4 3
—
CMDLOG3 CMDLOG2 CMDLOG1 CMDLOG0
0 —
R R
R R
Rev. 3.0, 04/02, page 851 of 1064
25 24
— —
0 0
R R
R R
17 16
— — —
0 0
R R
R R
9
— — —
0 0
R R
R R
2 1
— — —
R R
R R
0
R
R
0
R
R
8
0
R
R
0
R
R