I/O Map - Nokia 9000i Service Manual

After Sales
Technical Documentation
Signal name
PWRGOOD
5VPDX
TESTMODEX (Input)
IRSHD
RSSHDX
RSENX
XPWRON
FLASHPD1X
FLASHPD2X
FLASHWP1X
FLASHWP2X
LCDVCCON
LCDVEEON
DISPON
"LID"
VL1

I/O map

All chipselects are generated in the E3G.
Device
PIC0
PIC0
Timers 0 – 2
Port B
RTC Offset
RTC Data
Port 92
PIC1
PIC1
COM2
COM1
DRAM controller
IRDA Select Register
Original, 08/96
Table 20. I/O usage on E3G CPU
E3G CPU pin
RESET#
PMI2 / P45
DTR0# / P02
RI1# / P13
DSR0# / P00
CTS0# / P04
PMI3 / P44
SUSPEND#
RI0# / P03
DCD0# / P01
CTS1# / P15
LCDVCCON
LCDVEEON
DISPON
PMI0
PMI1
Table 21. I/O Map
Address
0020 – 0021
F022h
0040h – 0043h
0061h
0070h
0071h
0092h
00A0h – 00A1h
F0A2h
02F8h – 02FF
03F8h – 03FF
F300h – F323h
F3F8h – F3F9h
Polarity
H = Power good
L = Shut down
L = Test mode
H = Shut down
L = Shut down
L = Enabled
H (pulse) => CMT ON
L = Shut down
L = Shut down
L = Protected
L = Protected
H = Vcc ON
H= Vee ON
H = Display ON
H = Lid open
H = CMT ON
Standard PC compatible
Edge / Level control E3G Spe-
cific
Standard PC compatible
Standard PC compatible
Standard PC compatible
Standard PC compatible
Standard PC compatible
Standard PC compatible
Edge / Level control E3G Spe-
cific
Standard PC compatible
Standard PC compatible
E3G Specific
E3G Specific
RAE/RAK–1N
PDA Hardware
Reset value
– (In)
L
– (In)
H
H
H
L
H
H
H
H
L
L
L
– (In)
– (In)
Note
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