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coded data on a convolutional coder is called the "coding constraint
length," and is two in the case of the coder in Fig. 5-49.
The sum of modulo 2 is taken.
Input data
The sum of modulo 2 is taken.
Fig. 5-49 Convolutional Coder
Here, let's describe the regularity of the coded output data on the input data
on a convolutional coder. In the coder in Fig. 5-49, the combinations of
two bits 00, 10, 01 and 11 currently stored in the shift register can each be
expressed by four states A, B, C and D. At this time, the relationship
between these four states and one bit of input data can be expressed as the
shift in states in Fig. 5-50. For example, in this figure, if the state of the
shift register is A and 0 is input as the input data, coded data 00 is output,
and the state remains at A. When 1 is added to the input data, coded data
11 is output which means that the state will shift to state B. In other words,
from state A the state shifts only to state A or to state B.
The shift in states of other states B, C and D also have the same nature.
10
01
D
B
A
11
00
Fig. 5-50 Shift in States of Convolutional Coder
In Fig. 5-50, when input data is "0" for each of the internal states A, B, C
and D of the shift register, the shift in state is expressed by the solid line,
and when input data is "1", the shift in state is expressed by the dotted line.
The data of two bits shown on the solid line or dotted line shows the coded
G3 FACSIMILE COMMUNICATIONS
[2]
Shift register
[1]
01
10
C
00
11
Coded
output data
Shift register states
A: 00
B: 10
C: 01
D: 11
: Shift when input
data is "0"
: Shift when input
data is "1"
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