Mitsubishi Electric MELSEC iQ-R Series User Manual page 36

Device name (device)
Link direct device Link input (Jn\X)
Link output (Jn\Y)
Link relay (Jn\B)
Link special relay (Jn\SB)
Link register (Jn\W)
Link special register
(Jn\SW)
Module access Module access device/
device intelligent function module
device (Un\G)
Multiple CPU shared
device (U3En\G)
CPU buffer CPU buffer memory
memory access access device (U3En\G)
device
CPU buffer memory
access device (fixed cycle
communication area)
(U3En\HG)
Refresh data register (RD)
*1 Process CPUs and safety CPUs do not support high-speed access.
*2 Safety devices cannot be accessed.
*3 Q12DCCPU-V (Basic mode) has no device.
*4 A device name for QCPUs (Q mode) and LCPUs
*5 RnENCPUs and safety CPUs have no device.
2 SPECIFICATIONS
34
2.2 Access Specifications for a CPU Module
Access target device type (series)
RCPU
Programmable controller
*1
CPU/Process CPU /Safety
*1*2
CPU
General High-speed
access access
 
 
 
 
 
 
 
 
 
*5
 
 
QCPU (Q mode)
C Controller Programma
module ble
controller
CPU/
Process
CPU
 
 
 
 
 
 
 
 
 
 
 
LCPU
C Controller Programma
module ble
controller
CPU
 
 
 
 
 
 
 
 
 
 
 