Mitsubishi Electric MELSEC iQ-R Series User Manual page 34

Device name (device)
Link special register (SW)
Step relay (S)
Direct input (DX)
Direct output (DY)
*5
Index register (Z, V )
Long index register (LZ)
File register (R)
(ZR)
(ERn\R)
Link direct Link input (Jn\X)
device
Link output (Jn\Y)
Link relay (Jn\B)
Link special relay
(Jn\SB)
Link register (Jn\W)
Link special register
(Jn\SW)
Module Module access
access device device/intelligent
function module
device (Un\G)
Multiple CPU
shared device
(U3En\G)
CPU buffer CPU buffer memory
memory access device
access device (U3En\G)
CPU buffer memory
access device
(fixed cycle
communication
area) (U3En\HG)
Refresh data register (RD)
*1 Process CPUs and safety CPUs do not support high-speed access.
*2 Safety devices cannot be accessed.
*3 Q12DCCPU-V (Basic mode) has no device.
*4 A device name for QCPUs (Q mode) and LCPUs
*5 Can be set only for FXCPUs.
*6 RnENCPUs and safety CPUs have no device.
2 SPECIFICATIONS
32
2.2 Access Specifications for a CPU Module
Access target device type (series)
RCPU
Programmable C
controller CPU/ Controller
*1
Process CPU /Safety module
*1*2
CPU
General High-
access speed
access
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
*6
  
  
QCPU (Q mode) LCPU
Program C Program
mable Controller mable
controller module controller
CPU/ CPU
Process
CPU
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
FX5CPU FXCPU
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 