Top-Level Block Diagram; Zynq Ultrascale+ Rfsoc Top-Level Block Diagram - Xilinx Zynq UltraScale+ ZCU216 User Manual

Top-Level Block Diagram

Processing System
RPU
Cortex-R5
32 KB I/D
128 KB TCM
Low Power Switch
256 KB
RGMII
4 x 1GE
ULPI
2 x USB 3.0
NAND x8
ONFI 3.1
2 x SD3.0/
eMMC4.51
Quad-SPI
2 x CAN
2 x UART
SYSMON
CSU
SHA3
AES-GCM
RSA
Battery
Low Power
Power
UG1390 (v1.1) July 10, 2020
ZCU216 Board User Guide
Figure 4: Zynq UltraScale+ RFSoC Top-Level Block Diagram
APU
GIC
Cortex-A53
32 KB I/D
Cortex-R5
32 KB I/D
128 KB TCM
ACP
OCM
x 8
2 x SPI
2 x I2C
LPD-DMA
GPIOs
PMU
Processor
System BPU
128 KB RAM DDRC (DDR4/3/3L, LPDDR3/4)
Full Power
Chapter 3: Board Component Descriptions
GIC
Cortex-A53 Cortex-A53 Cortex-A53
32 KB I/D 32 KB I/D 32 KB I/D
SCU
1 MB L2
SMMU/CCI
Central
Switch
FPD-DMA
32-bit/64-bit
M
64-bit
Send Feedback
PCIe Gen2
x1, x2, or x4
2 x SATA
v3.1
SGMII
USB 3.0
DisplayPort
v1.2 x1, x2
Programmable
Logic
100G
Interlaken
Ethernet
GFC
GTY GTH
Quad Quad
PCIe
To ACP
Gen4
S M S
128-bit
X23309-031220
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