Block Diagram; Board Features - Xilinx Zynq UltraScale+ ZCU208 User Manual

Block Diagram

A block diagram of the ZCU208 evaluation board is shown in the following figure.
RFMC CONN. 2
DAC_T3_CH[0,2]
DAC_T2_CH[0,2]
DAC_T1_CH[0,2]
DAC_T0_CH[0,2]
DAC_CLK (SMA)
SYSMON
Header
RFMC CONN. 1
ADC_T3_CH[0,2]
ADC_T2_CH[0,2]
ADC_T1_CH[0,2]
ADC_T0_CH[0,2]
ADC_CLK (SMA)
ADCIO
GPIO_DIP_SW[6:7]
CPU_RESET

Board Features

The ZCU208 evaluation board features are listed here. Detailed information for each feature is
provided in Chapter 3: Board Component
UG1410 (v1.0) July 8, 2020
ZCU208 Board User Guide
Figure 1: Evaluation Board Block Diagram
CLK104 CONN. Banks
67.68.84.87.226.228
DACIO[00:15]
DAC
69
CLK
87
DAC
231
DAC
230
DAC
229
DAC
XCZU48DR-2FSVG1517
228
0
ADC
227
ADC
226
ADC
225
ADC
224
ADC
84 64 65
CLK
FMCP HSPC
DDR4 Component
LA[17:33]
32-bit (4x8-bit)
GPIO_DIP_SW[2:3[
C0 Interface
GPIO_LED
MPS430_GPIO
SFP[0:3]_TX_DISABLE
UART2
MSP430_UCA1
Descriptions.
DDR4 Component
32-bit (4x8-bit)
C1 Interface
GPIO_DIP_SW[0:1]
FMCP HSPC
8A34001_GPIO[0:7]
8A34001_GPIO[10:15]
FMCP HSPC Sync
PL_I2C0
PL_I2C1
MGTY
68 67
131
MGTY
130
MGTY
129
MGTY
128
PS GTR
505
PS DDR 504
PS
66
500
PS PB/LED DDR4 SODIMM
UART0 64-bit
PS_I2C0
PS_12C1
QSPI LWR
QSPI UPR
Send Feedback
Chapter 1: Introduction
MSP430
LA[00:16]
System
Controller
GPIO_SW
SD 3.0
PS_PMU_GPO[0:5]
USB0 3.0
ETHERNET RGMII
CONFIG. IF
JTAG IF
FMCP_HSPC_DP[4:7]
FMCP_HSPC_DP[0:3]
USER_MGT_CLK
(SMA)
SFP[2:3]
SFP[0:1]
USB0 3.0
SATA1 M.2
X23790-040220
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