Quad-Spi Flash Memory (Mio 0–12) - Xilinx Zynq UltraScale+ ZCU216 User Manual

Table 7: MIO Peripheral Mapping (cont'd)
MIO[0:25] Bank 500
14
15
16
17
18 UART0
19 UART0
20 Not assigned/no connect
21 Not assigned/no connect
22
23
24 Not assigned/no connect
25 Not assigned/no connect
Quad-SPI Flash Memory (MIO 0–12)
[Figure 2, callout 5]
The Micron dual MT25QU02GCBB8E12-0SIT serial NOR flash Quad-SPI memories are capable
of holding the boot image for the Zynq UltraScale+ RFSoC. This interface is used to support
QSPI32 boot mode as defined in the Zynq UltraScale+ Device Technical Reference Manual
(UG1085).
The dual Quad-SPI flash memory located at U11/U12 provides 4 Gb of non-volatile storage that
can be used for configuration and data storage.
• Part number: MT25QU02GCBB8E12-0SIT (Micron)
• Description:
2 Gb/256 MB
○
2.7V – 3.6V 24-ball TBGA
○
90 MHz DTR/133 MHz STR
○
• Datapath width: 8 bits
• Data rate: Various depending on Single/Dual/Quad mode
The configuration and Quad-SPI section of the Zynq UltraScale+ Device Technical Reference Manual
(UG1085) provides details on using the Quad-SPI flash memory. For more QSPI details, see the
Micron MT25QU02GCBB8E12-0SIT data sheet on the
The detailed RFSoC connections for the feature described in this section are documented in the
ZCU216 board XDC file, referenced in
UG1390 (v1.1) July 10, 2020
ZCU216 Board User Guide
MIO[26:51] Bank 501
I2C0 40
I2C0 41
I2C1 42
I2C1 43
44
45
46
47
GPIO 48
GPIO 49
50
51
Appendix B: Xilinx Design
Chapter 3: Board Component Descriptions
SD1
SD1
SD1
Not assigned/no connect
Not assigned/no connect
SD1
SD1
SD1
SD1
SD1
SD1
SD1
Micron Technology
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MIO[52:77] Bank 502
66 GEM3
67 GEM3
68 GEM3
69 GEM3
70 GEM3
71 GEM3
72 GEM3
73 GEM3
74 GEM3
75 GEM3
76 MDIO3
77 MDIO3
website.
Constraints.
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