Ps Gtr Transceivers; Ps M.2 Sata Connector - Xilinx Zynq UltraScale+ ZCU216 User Manual

For additional information on GTY transceivers, see the UltraScale Architecture GTY Transceivers
User Guide (UG578).
The detailed RFSoC connections for the feature described in this section are documented in the
ZCU216 board XDC file, referenced in

PS GTR Transceivers

The PS-side GTR transceiver Bank 505 supports USB (3.0) and SATA, with two channels not
used.
Bank 505 USB0 lane 2 supports the USB0 (USB3.0) interface documented in the USB 3.0
Transceiver and USB 2.0 ULPI PHY section. The PS-Side GTR transceiver is used to provide USB
3.0 Host-Only connectivity.
Bank 505 SATA lane 3 supports SATA connector U36 shown in
Bank 505 reference clocks are connected to the U43 SI5341B clock generator as detailed in
SI5341B 10 Independent Output Any-Frequency Clock Generator
The detailed RFSoC connections for the feature described in this section are documented in the
ZCU216 board XDC file, referenced in

PS M.2 SATA Connector

[Figure 2, callout 31 and 32]
The M.2 SATA interface is provided for SATA SSD access using the PS-Side bank 505 GTR
transceiver. The following figure shows M.2 connector U36.
The Socket 2 SATA adapter pinout with Key M is shown in the table below. SATA-A data
connection is used for TX and SATA-B for RX. The M.2 connector U36 is a type 2242 (active
component section 22 mm wide with overall length 42 mm form factor) used on Socket 2.
UG1390 (v1.1) July 10, 2020
ZCU216 Board User Guide
Chapter 3: Board Component Descriptions
Appendix B: Xilinx Design
Appendix B: Xilinx Design
Constraints.
Figure 18: M.2 Connector.
U43.
Constraints.
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