Fmcp Hspc; Zsfp+; Zcu216 Zu49Dr Gty Mapping - Xilinx Zynq UltraScale+ ZCU216 User Manual

Table 21: ZCU216 ZU49DR GTY Mapping
ZU49DR-FFVF1760

FMCP HSPC

Eight MGTs are provided by PL-side MGT banks 130 and 131. Available MGT reference clocks
include the FMC defined GBT clocks 0 and 1, a programmable SI570 clock and a differential SMA
clock.

zSFP+

Four MGTs are provided by PL-side MGT banks 128 and 129 for the quad (2x2 connector) zSFP+
interface. Available GTY reference clocks include two sets of clocks to/from IDT 8A34001 U409.
Each zSFP+ connector provides an I2C based control interface. This I2C interface is accessible for
each individual zSFP+ module through the I2C multiplexer topology on the ZCU216.
UG1390 (v1.1) July 10, 2020
ZCU216 Board User Guide
ZCU216 ZU49DR-FFVF1760 GTY Mapping
8A34001 CLK1_IN - Q1_OUT
NO CONNECT
zSFP1
zSFP0
8A34001 Q11_OUT
8A34001 CLK5_IN
CoreHC2 1x8 Connector
NO CONNECT
zSFP3
zSFP2
8A34001 Q7_OUT
8A34001 CLK6_IN
FMC DP3
FMC DP2
FMC DP1
FMC DP0
USER_SMA_MGT_CLOCK
FMC GBTCLK0 M2C
FMC DP7
FMC DP6
FMC DP5
FMC DP4
USER_MGT_SI570_CLOCK
FMC GBTCLK1 M2C
Chapter 3: Board Component Descriptions
ch3
ch2
ch1
GTY Quad 128
ch0
refclk1
refclk0
ch3
ch2
ch1
GTY Quad 129
ch0
refclk1
refclk0
ch3
ch2
ch1
GTY Quad 130
ch0
refclk1
refclk0
ch3
ch2
ch1
GTY Quad 131
ch0
refclk1
refclk0
Send Feedback
PCIe4
CMAC
ILKN
PCIe4
www.xilinx.com
55