Mitsubishi Electric MELSEC Q Series Reference Manual page 391

APPENDICES
Number Name Meaning
Power
supply off Power supply off
SD1780
detection detection status
status
Power
supply Power supply failure
SD1781
failure detection status
detection
Momentary
power
failure Momentary power
SD1782 detection failure detection count
counter for for power supply 1
power
supply 1*1
Momentary
power
failure Momentary power
SD1783 detection failure detection count
counter for for power supply 2
power
supply 2*1
*1: The "power supply 1" indicates the redundant power supply module mounted on the POWER 1 slot of the redundant base unit (Q3 RB/Q6 RB/Q6 WRB).
The "power supply 2" indicates the redundant power supply module mounted on the POWER 2 slot of the redundant base unit (Q3 RB/Q6 RB/Q6 WRB).
*2: This applies to modules whose serial No. (first five digits) is "07032" or later.
However, for the multiple CPU system configuration, this applies to all CPU modules whose serial No. (first five digits) is "07032" or later.
*3: This applies to modules with a serial number (first five digits) of "10042" or later.
App - 49
(6) Redundant power supply module information
The special register (SD1780 to SD1789) is valid only for redundant power
supply systems. All bits are set to "0" for single power supply systems.
Special Register List
• This register stores status of a redundant power supply module
(Q6 RP) with input power off, in the following bit pattern.
• When the main base unit is not a redundant power main base
unit (Q3 RB), "0" is stored.
Input power OFF
detection status of
power supply 2
to
b15
to
SD1780
• In a multiple CPU system, the status is stored only to CPU
module No.1.
• This register stores failure detection status of a redundant power
supply module (Q6 RP) in the following bit pattern. (After a
failure is detected on a redundant power supply module, the bit
corresponding to the failed module turns to "0" upon turning off
the module.)
• When the main base unit is not a redundant power main base
unit (Q3 RB), "0" is stored.
Failure detection
status of power
supply 2 *1
to
b15
SD1781 to
• In a multiple CPU system, the status is stored only to CPU
module No.1.
• This register counts the number of times of momentary power
failure of the power supply 1/2.
• This register monitors the status of the power supply 1/2
mounted on a redundant power main base unit (Q3 RB) and
counts the number of momentary power failures.
The status of power supply 1/2 mounted on the extension base
unit for redundant power supply system and the redundant type
extension base unit is not monitored.
• When the CPU module starts, the counter of the power supply
1/2 is cleared to "0".
• If the input power to one of the redundant power supply modules
is turned off, the corresponding counter is cleared to "0".
• The counter is incremented by one upon momentary power
failure on the power supply 1 or 2.
• When the main base unit is not a redundant power main base
unit (Q3 RB), "0" is stored.
• In a multiple CPU system, the status is stored only to CPU
module No.1.
• The counter repeats increment and decrement of the value;
0→32767→-32768→0. (The value is displayed within the range
of 0 to 65535 on the device monitor window of GX Developer.)
Explanation
Input power OFF
Each bit
detection status of
power supply 1 0: Input power ON status/ No
*1 *1
redundant power supply
module
to
b9 b8 b7 b1 b0
1: Input power OFF status
to
Main base unit
Extension base unit 1st stage
Extension base unit 7th stage
Main base unit
Extension base unit 1st stage
Extension base unit 7th stage
Failure detection
Each bit
status of power
0: Redundant power supply
supply 1 *1
module failure not
detected/No redundant power
to
b9 b8 b7 b1 b0
supply module
to
1: Redundant power supply
module failure detected
(Detectable for redundant
power supply module only)
Main base unit
Extension base unit 1st stage
Extension base unit 7th stage
Main base unit
Extension base unit 1st stage
Extension base unit 7th stage
MELSEC-Q
Corresponding
Set by Corresponding
ACPU
(When set)
D9
S (Every
END New
processing)
S (Every
END New
processing)
S (Every
END New
processing)
S (Every
END New
processing)
App - 49
CPU
Qn(H) *2
*2
QnPH
QnPRH
Rem
*3
QnU