Mitsubishi Electric MELSEC Q Series Reference Manual page 385

APPENDICES
Number Name Meaning
Status of Status of CPU
SD200
switch switch
App - 43
(2) System information
Special Register List
• This register stores the status of the remote I/O module switch in the
following bit pattern.
B15
Empty
Remote I/O module switch status
1
• This register stores the status of the CPU module switches in the
following bit pattern.
B15
B12B11
3
: CPU switch status
1
: Memory card switch
2
: DIP switch
 3
• This register stores the status of the CPU module switches in the
following bit pattern.
B15
Empty
: CPU switch status
1
: Memory card switch
2
• This register stores the status of the CPU module switches in the
following bit pattern.
B15
Empty
: CPU switch status
1
: Memory card switch
2
• This register stores the status of the CPU module switches in the
following bit pattern.
B15
B12B11
3
: CPU key
1

State of switch
: Memory card switch
2

: DIP switch
3

Explanation
B4 B3
1
Always 1: STOP
B8 B7 B4 B3
Empty
2 1
0: RUN
1: STOP
2: L.CLR
Always OFF
B8 through B12 correspond to SW1
through SW5 of system setting
switch 1.
0: OFF, 1: ON
BD through BF are empty.
B6 B5 B4 B3
2 1
0: RUN
1: STOP
Always OFF
B6 B5 B4 B3
2
1
0: RUN
1: STOP
Always OFF
B8 B7 B4 B3
Empty
2
1
0 : RUN
1 : STOP
2 : L.CLR
B4: card A, B5: card B,
0: OFF, 1: ON
B8 through B12 correspond to SW1
through SW5 of system setting
switch 1.
B14 and B15 correspond to SW1
and SW2 of system setting switch
2.
0: OFF, 1: ON
MELSEC-Q
Corresponding
Set by
ACPU
(When set)
D9
B0
S (Always) New
B0
S (Every
END New
processing)

B0
S (Every
END New
processing)
S (when
B0
RUN/
STOP/
New
RESET
switch
changed)
B0

S (Every
END New

processing)

Corresponding
CPU
Rem
Qn(H)
QnPH
QnPRH
Q00J/Q00/Q01
QnU
QnA
App - 43