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S3C8248/C8245/P8245/C8247/C8249/P8249
TACON
— Timer A Control Register
Bit Identifier
RESET Value
RESET
Read/Write
Addressing Mode
.7–.6
.5–.4
.3
.2
.1
.0
.7
.6
0
0
R/W
R/W
Register addressing mode only
Timer A Input Clock Selection Bits
0
0
fxx/1024
0
1
fxx/256
1
0
fxx/64
1
1
External clock (TACLK)
Timer A Operating Mode Selection Bits
0
0
Internal mode (TAOUT mode)
0
1
Capture mode (capture on rising edge, counter running, OVF can occur)
1
0
Capture mode (capture on falling edge, counter running, OVF can occur)
1
1
PWM mode (OVF interrupt can occur)
Timer A Counter Clear Bit
0
No effect
1
Clear the timer A counter (when write)
Timer A Overflow Interrupt Enable Bit
0
Disable overflow interrupt
1
Enable overflow interrupt
Timer A Match/Capture Interrupt Enable Bit
0
Disable interrupt
1
Enable interrupt
Timer A Match/Capture Interrupt Pending Bit
0
No interrupt pending
0
Clear pending bit (write)
1
Interrupt is pending
.5
.4
0
0
R/W
R/W
R/W
CONTROL REGISTER
EDH
Set 1, Bank 0
.3
.2
.1
0
0
0
R/W
R/W
.0
0
R/W
4-41
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