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S3C8248/C8245/P8245/C8247/C8249/P8249
BITC
— Bit Complement
BITC
dst.b
dst(b) ← NOT dst(b)
Operation:
This instruction complements the specified bit within the destination without affecting any other
bits in the destination.
Flags:
C: Unaffected.
Z: Set if the result is "0"; cleared otherwise.
S: Cleared to "0".
V: Undefined.
D: Unaffected.
H: Unaffected.
Format:
opc
NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b'
Example:
Given: R1 = 07H
BITC
If working register R1 contains the value 07H (00000111B), the statement "BITC R1.1"
complements bit one of the destination and leaves the value 05H (00000101B) in register R1.
Because the result of the complement is not "0", the zero flag (Z) in the FLAGS register (0D5H)
is cleared.
dst | b | 0
is three bits, and the LSB address value is one bit in length.
→
R1.1
R1 = 05H
Bytes
Cycles
Opcode
2
4
INSTRUCTION SET
Addr Mode
(Hex)
dst
57
rb
6-19
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