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3.5.2
MMU Software Management .............................................................................. 45
3.5.3
MMU Instruction (LDTLB) ................................................................................ 45
3.5.4
Hardware ITLB Miss Handling ........................................................................... 46
3.5.5
Avoiding Synonym Problems.............................................................................. 47
3.6
MMU Exceptions.............................................................................................................. 48
3.6.1
Instruction TLB Multiple Hit Exception.............................................................. 48
3.6.2
Instruction TLB Miss Exception.......................................................................... 49
3.6.3
Instruction TLB Protection Violation Exception ................................................. 50
3.6.4
Data TLB Multiple Hit Exception ....................................................................... 51
3.6.5
Data TLB Miss Exception ................................................................................... 51
3.6.6
Data TLB Protection Violation Exception........................................................... 52
3.6.7
Initial Page Write Exception................................................................................ 53
3.7
Memory-Mapped TLB Configuration .............................................................................. 54
3.7.1
ITLB Address Array ............................................................................................ 55
3.7.2
ITLB Data Array 1 .............................................................................................. 56
3.7.3
ITLB Data Array 2 .............................................................................................. 57
3.7.4
UTLB Address Array .......................................................................................... 57
3.7.5
UTLB Data Array 1 ............................................................................................. 59
3.7.6
UTLB Data Array 2 ............................................................................................. 60
4.1
Overview .......................................................................................................................... 61
4.1.1
Features................................................................................................................ 61
4.1.2
Register Configuration......................................................................................... 62
4.2
Register Descriptions........................................................................................................ 62
4.3
Operand Cache (OC) ........................................................................................................ 65
4.3.1
Configuration....................................................................................................... 65
4.3.2
Read Operation .................................................................................................... 66
4.3.3
Write Operation ................................................................................................... 67
4.3.4
Write-Back Buffer ............................................................................................... 69
4.3.5
Write-Through Buffer.......................................................................................... 69
4.3.6
RAM Mode.......................................................................................................... 69
4.3.7
OC Index Mode ................................................................................................... 70
4.3.8
Coherency between Cache and External Memory............................................... 71
4.3.9
Prefetch Operation............................................................................................... 71
4.4
Instruction Cache (IC) ...................................................................................................... 72
4.4.1
Configuration....................................................................................................... 72
4.4.2
Read Operation .................................................................................................... 73
4.4.3
IC Index Mode..................................................................................................... 74
4.5
Memory-Mapped Cache Configuration ............................................................................ 74
4.5.1
IC Address Array................................................................................................. 74
4.5.2
IC Data Array ...................................................................................................... 75
4.5.3
OC Address Array ............................................................................................... 76
................................................................................................................ 61
Rev. 2.0, 03/99, page viii of 13
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