Table 8.3
Execution Cycles (cont)
Functional
Category
No.
Instruction
Fixed-point
63
DIV0U
arithmetic
64
DIV1
instructions
65
DMULS.L Rm,Rn
66
DMULU.L Rm,Rn
67
DT
68
MAC.L
69
MAC.W
70
MUL.L
71
MULS.W
72
MULU.W
73
NEG
74
NEGC
75
SUB
76
SUBC
77
SUBV
Logical
78
AND
instructions
79
AND
80
AND.B
81
NOT
82
OR
83
OR
84
OR.B
85
TAS.B
86
TST
87
TST
88
TST.B
89
XOR
90
XOR
91
XOR.B
Instruc-
tion
Group
EX
Rm,Rn
EX
CO
CO
Rn
EX
@Rm+,@Rn+
CO
@Rm+,@Rn+
CO
Rm,Rn
CO
Rm,Rn
CO
Rm,Rn
CO
Rm,Rn
EX
Rm,Rn
EX
Rm,Rn
EX
Rm,Rn
EX
Rm,Rn
EX
Rm,Rn
EX
#imm,R0
EX
#imm,@(R0,GBR) CO
Rm,Rn
EX
Rm,Rn
EX
#imm,R0
EX
#imm,@(R0,GBR) CO
@Rn
CO
Rm,Rn
MT
#imm,R0
MT
#imm,@(R0,GBR) CO
Rm,Rn
EX
#imm,R0
EX
#imm,@(R0,GBR) CO
Execu-
Issue
tion
Rate
Latency
Pattern Stage Start Cycles
1
1
#1
1
1
#1
2
4/4
#34
2
4/4
#34
1
1
#1
2
2/2/4/4
#35
2
2/2/4/4
#35
2
4/4
#34
2
4/4
#34
2
4/4
#34
1
1
#1
1
1
#1
1
1
#1
1
1
#1
1
1
#1
1
1
#1
1
1
#1
4
4
#6
1
1
#1
1
1
#1
1
1
#1
4
4
#6
5
5
#7
1
1
#1
1
1
#1
3
3
#5
1
1
#1
1
1
#1
4
4
#6
Rev. 2.0, 03/99, page 169 of 396
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