Pair Single-Precision Data Transfer - Hitachi SH7750 Programming Manual

High-performance risc engine superh (sh) 32-bit risc mcu/mpu series
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the FPU state. With the FRCHG instruction, an FPSCR.FR bit modification can be performed in
one cycle.
6.6.2

Pair Single-Precision Data Transfer

In addition to the powerful new geometric operation instructions, the SH7750 also supports high-
speed data transfer instructions.
When FPSCR.SZ = 1, the SH7750 can perform data transfer by means of pair single-precision
data transfer instructions.
• FMOV DRm/XDm, DRn/XDRn (m, n: 0, 2, 4, 6, 8, 10, 12, 14)
• FMOV DRm/XDm, @Rn (m: 0, 2, 4, 6, 8, 10, 12, 14; n: 0 to 15)
These instructions enable two single-precision (2 × 32-bit) data items to be transferred; that is, the
transfer performance of these instructions is doubled.
• FSCHG
This instruction changes the value of the SZ bit in FPSCR, enabling fast switching between
use and non-use of pair single-precision data transfer.
Rev. 2.0, 03/99, page 128 of 396

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