Hitachi SH7750 Programming Manual page 249

High-performance risc engine superh (sh) 32-bit risc mcu/mpu series
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Example 4
MOV
R2,R3
ROTCL
R3
SUBC
R1,R1
XOR
R3,R3
SUBC
R3,R2
DIV0S
R0,R1
.arepeat
32
ROTCL
R2
DIV1
R0,R1
.aendr
ROTCL
R2
ADDC
R3,R2
;R2 (32 bits) ÷ R0 (32 bits) = R2 (32 bits); signed
;
;
;Dividend sign-extended to 64 bits (R1:R2)
;R3 = 0
;If dividend is negative, subtract 1 to convert to one's complement notation
;Flag initialization
;
;Repeat 32 times
;
;
;R2 = quotient (one's complement notation)
;If MSB of quotient is 1, add 1 to convert to two's complement notation
;R2 = quotient (two's complement notation)
Rev. 2.0, 03/99, page 235 of 396

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