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Table 1.1
SH7750 Features
Item
LSI
CPU
Rev. 2.0, 03/99, page 2 of 396
Features
•
Operating frequency: 200 MHz
•
Performance:
360 MIPS (200 MHz)
1.4 GFLOPS (200 MHz)
•
Superscalar architecture: Parallel execution of two instructions
•
Voltage: 1.8 V (internal), 3.3 V (I/O)
•
Packages: 256-pin BGA, 208-pin QFP
•
External buses
Separate 26-bit address and 64-bit data buses
External bus frequency of 1/2, 1/3, 1/4, 1/6, or 1/8 times internal bus
frequency
•
Original Hitachi SH architecture
•
32-bit internal data bus
•
General register file:
Sixteen 32-bit general registers (and eight 32-bit shadow registers)
Seven 32-bit control registers
Four 32-bit system registers
•
RISC-type instruction set (upward-compatible with SH Series)
Fixed 16-bit instruction length for improved code efficiency
Load-store architecture
Delayed branch instructions
Conditional execution
C-based instruction set
•
Superscalar architecture (providing simultaneous execution of two
instructions) including FPU
•
Instruction execution time: Maximum 2 instructions/cycle
•
Virtual address space: 4 Gbytes (448-Mbyte external memory space)
•
Space identifier ASIDs: 8 bits, 256 virtual address spaces
•
On-chip multiplier
•
Five-stage pipeline
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