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Section 8 Pipelining
The SH7750 is a 2-ILP (instruction-level-parallelism) superscalar pipelining microprocessor.
Instruction execution is pipelined, and two instructions can be executed in parallel. The execution
cycles depend on the implementation of a processor. Definitions in this section may not be
applicable to SH-4 Series models other than the SH7750.
8.1
Pipelines
Figure 8.1 shows the basic pipelines. Normally, a pipeline consists of five or six stages: instruction
fetch (I), decode and register read (D), execution (EX/SX/F0/F1/F2/F3), data access (NA/MA),
and write-back (S/FS). An instruction is executed as a combination of basic pipelines. Figure 8.2
shows the instruction execution patterns.
Rev. 2.0, 03/99, page 149 of 396
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