Motorola DSP56367 User Manual page 519

24-bit digital signal processor
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I
2
I
C, 1-14, 9-1, 9-19
Bit Transfer, 9-19
Bus Protocol For Host Read Cycle, 9-22
Bus Protocol For Host Write Cycle, 9-21
Data Transfer Formats, 9-21
Master Mode, 9-27
Protocol for Host Write Cycle, 9-21
Receive Data In Master Mode, 9-28
Receive Data In Slave Mode, 9-25
Slave Mode, 9-24
Start and Stop Events, 9-20
Transmit Data In Master Mode, 9-28, 9-28
Transmit Data In Slave Mode, 9-26, 9-26
2
I
C Bus Acknowledgment, 9-20
2
I
C Mode, 9-1
IEC958, 1-14, 12-1
Inter Integrated Circuit Bus, 1-14, 9-1
internal buses, 1-8
internal clocks, 3-6
Internal Exception Priorities
SHI, 9-7
interrupt, 1-8
interrupt and mode control, 2-1, 2-1, 2-8, 2-8, 2-9
interrupt control, 2-8, 2-8, 2-9
interrupt timing, 3-9
external level-sensitive fast, 3-14
external negative edge-triggered, 3-15
Interrupt Vectors
SHI, 9-7
INV, 13-9
J
Jitter, 4-5
JTAG, 1-10, 1-10, 2-21
JTAG Port
timing, 3-75, 3-76
JTAG/OnCE port, 2-1, 2-1
L
LA register, 1-8
LC register, 1-8
Loop Address register (LA), 1-8
Loop Counter register (LC), 1-8
M
MAC, 1-6
Manual Conventions, iii, iii
maximum ratings, 3-1, 3-2
mechanical drawings, 14-8
memory
MOTOROLA
Index
expansion, 1-11
external expansion port, 1-11
off-chip, 1-11
on-chip, 1-10, 1-10
Mfax system, 14-8
mode control, 2-8, 2-8, 2-9
Mode select timing, 3-9
modulo adder, 1-7
multiplexed bus timings
read, 3-52
write, 3-53
multiplier-accumulator (MAC), 1-5, 1-6
N
non-multiplexed bus timings
read, 3-50
write, 3-51
O
offset adder, 1-7
OMR register, 1-8
OnCE module, 1-10, 2-21
On-Chip Emulation (OnCE) module, 1-10
on-chip memory, 1-10
Operating Mode Register (OMR), 1-8
operating mode select timing, 3-15
ordering drawings, 14-8
P
PAB, 1-9
package
TQFP description, 14-1, 14-5
PAG, 1-7
PC register, 1-8
PC0-PC20 bits, 13-6
PCE, 13-11
PCU, 1-7
PDB, 1-8
PDC, 1-7
Peripheral I/O Expansion Bus, 1-8
Phase Lock Loop, 3-8
PIC, 1-7
PL0-PL20 bits, 13-5
PL21-PL22 bits, 13-5
PLL, 1-9, 2-1, 2-1, 2-5, 3-8
Characteristics, 3-8
performance issues, 4-5
PLL design considerations, 4-5, 4-5
PLL performance issues, 4-5
Port A, 2-1, 2-1, 2-6
Port B, 2-1, 2-1, 2-11, 2-11, 2-12, 2-12, 7-1
Port C, 2-1, 2-1, 2-15, 2-15, 2-19, 7-2, 7-2
Index-3

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