Hpcr Host Chip Select Polarity (Hcsp) Bit 13 - Motorola DSP56367 User Manual

24-bit digital signal processor
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Host Interface (HDI08)
HDI08 – DSP-Side Programmer's Model
8.5.6.14

HPCR Host Chip Select Polarity (HCSP) Bit 13

If the HCSP bit is cleared, the chip select (HCS) signal is configured as an active low input
and the HDI08 is selected when the HCS signal is low. If HCSP is set, HCS is configured as
an active high input and the HDI08 is selected when the HCS signal is high. This bit is ignored
in the multiplexed mode.
8.5.6.15
HPCR Host Request Polarity (HRP) Bit 14
The HRP bit controls the polarity of the host request signals. In the single host request mode
(HDRQ=0 in the ICR), if HRP is cleared and host requests are enabled (HREN=1 and HEN=1
in the HPCR), the HOREQ signal is an active low output. If HRP is set and host requests are
enabled, the HOREQ signal is an active high output.
In the double host request mode (HDRQ=1 in the ICR), if HRP is cleared and host requests
are enabled (HREN=1 and HEN=1 in the HPCR), the HTRQ and HRRQ signals are active
low outputs. If HRP is set and host requests are enabled, the HTRQ and HRRQ signals are
active high outputs.
8.5.6.16
HPCR Host Acknowledge Polarity (HAP) Bit 15
If the HAP bit is cleared, the host acknowledge (HACK) signal is configured as an active low
input, and the HDI08 drives the contents of the HIVR register onto the host bus when the
HACK signal is low. If HAP is set, HACK is configured as an active high input, and the
HDI08 outputs the contents of the HIVR register when the HACK signal is high.
8.5.7
DATA DIRECTION REGISTER (HDDR)
The HDDR controls the direction of the data flow for each of the HDI08 pins configured as
GPIO. Even when the HDI08 is used as the host interface, some of its unused signals may be
configured as GPIO pins. For information on the HDI08 GPIO configuration options, see
Section 8.6.8. If bit DRxx is set, the corresponding HDI08 pin is configured as an output
signal. If bit DRxx is cleared, the corresponding HDI08 pin is configured as an input signal.
See Table 8-6.
Figure 8-9 Host Data Direction Register (HDDR) (X:$FFFFC8)
15
14
13
12
DR15
DR14
DR13
DR12
8-16
11
10
9
8
DR11
DR10
DR9
DR8
DSP56367
7
6
5
4
DR7
DR6
DR5
DR4
3
2
1
0
DR3
DR2
DR1
DR0
MOTOROLA

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