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Serial Host Interface
Serial Host Interface Programming Model
9.5.5.4
HCKR Reserved Bits—Bits 23–14, 11
These bits in HCKR are reserved. They are read as zero and should be written with zero for
future compatibility.
9.5.5.5
HCKR Filter Mode (HFM[1:0]) — Bits 13–12
The read/write control bits HFM[1:0] specify the operational mode of the noise reduction
filters, as described in Table 9-3. The filters are designed to eliminate undesired spikes that
might occur on the clock and data-in lines and allow the SHI to operate in noisy environments
when required. One filter is located in the input path of the SCK/SCL line and the other is
located in the input path of the data line (i.e., the SDA line when in I
when in SPI master mode, and the MOSI line when in SPI slave mode).
Table 9-3 SHI Noise Reduction Filter Mode
HFM1
0
0
1
1
When HFM[1:0] = 00, the filter is bypassed (spikes are not filtered out). This mode is useful
when higher bit-rate transfers are required and the SHI operates in a noise-free environment.
When HFM[1:0] = 10, the narrow-spike-tolerance filter mode is selected. In this mode the
filters eliminate spikes with durations of up to 50ns. This mode is suitable for use in mildly
noisy environments and imposes some limitations on the maximum achievable bit-rate
transfer.
When HFM[1:0] = 11, the wide-spike-tolerance filter mode is selected. In this mode the filters
eliminate spikes up to 100 ns. This mode is recommended for use in noisy environments; the
bit-rate transfer is strictly limited. The wide-spike- tolerance filter mode is highly
recommended for use in I
improves noise immunity.
Note:
HFM[1:0] are cleared during hardware reset and software reset.
After changing the filter bits in the HCKR to a non-bypass mode (HFM[1:0] not equal to
'00'), the programmer should wait at least ten times the tolerable spike width before enabling
the SHI (setting the HEN bit in the HCSR). Similarly, after changing the HI
HCSR or the CPOL bit in the HCKR, while the filter mode bits are in a non-bypass mode
(HFM[1:0] not equal to '00'), the programmer should wait at least ten times the tolerable
spike width before enabling the SHI (setting HEN in the HCSR).
9-12
HFM0
0
Bypassed (Disabled)
1
Reserved
0
Narrow Spike Tolerance
1
Wide Spike Tolerance
2
C bus systems as it fully conforms to the I
DSP56367
2
C mode, the MISO line
Description
2
C bus specification and
2
C bit in the
MOTOROLA
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