GDB
24
TCSR
Control/Status
Register
9
Timer Control
Logic
TIO
CLK/2
prescaler CLK
(Timer 0
only)
13.3
TIMER/EVENT COUNTER PROGRAMMING MODEL
The DSP56367 views each timer as a memory-mapped peripheral with four registers
occupying four 24-bit words in the X data memory space. Either standard polled or interrupt
programming techniques can be used to service the timers. The timer programming model is
shown in Figure 13-3.
MOTOROLA
24
24
TLR
Load
Register
24
2
Counter
Figure 13-2 Timer Block Diagram
DSP56367
Timer/Event Counter Programming Model
24
TCR
Count
Register
24
24
Timer interrupt/
DMA request
Timer/ Event Counter
24
TCPR
Compare
Register
24
=
AA0676
13-3