Motorola DSP56367 User Manual page 172

Core Configuration
Operating Modes
The DSP starts fetching instructions beginning at address $C00000. Memory accesses are performed using SRAM
Mode 0 memory access type with 31 wait states and no address attributes selected. Address $C00000 is reflected as address
$00000 on Port A pins A0-A17.
The bootstrap program loads instructions through Port A from external byte-wide memory, connected to the least
significant byte of the data bus (bits 7-0), and starting at address P:$D00000. The bootstrap code expects to read 3 bytes
specifying the number of program words, 3 bytes specifying the address to start loading the program words and then 3
bytes for each program word to be loaded. The number of words, the starting address and the program words are read
Mode 1 least significant byte first followed by the mid and then by the most significant byte. The program words will be stored in
contiguous PRAM memory locations starting at the specified starting address. After reading the program words, program
execution starts from the same address where loading started.The SRAM memory access type is selected by the values in
Address Attribute Register 1 (AAR1), with 31 wait states for each memory access. Address $D00000 is reflected as
address $00000 on Port A pins A0-A17.
The DSP starts fetching instructions from the starting address of the on-chip Program ROM.
Mode 2
Reserved.
Mode 3
Reserved.
Mode 4
In this mode, the internal PRAM is loaded from the Serial Host Interface (SHI). The SHI operates in the SPI slave mode,
with 24-bit word width.The bootstrap code expects to read a 24-bit word specifying the number of program words, a
Mode 5 24-bit word specifying the address to start loading the program words and then a 24-bit word for each program word to be
loaded. The program words will be stored in contiguous PRAM memory locations starting at the specified starting
address. After reading the program words, program execution starts from the same address where loading started.
Mode 6 Same as Mode 5 except SHI interface operates in the I
Mode 7 Same as Mode 5 except SHI interface operates in the I
The DSP starts fetching instructions beginning at address $008000. Memory accesses are performed using SRAM
Mode 8
memory access type with 31 wait states and no address attributes selected.
Reserved. Used for Burn-In testing.
Mode 9
Reserved.
Mode A
Reserved.
Mode B
Instructions are loaded through the HDI08, which is configured to interface with an ISA bus. The HOST ISA bootstrap
code expects to read a 24-bit word specifying the number of program words, a 24-bit word specifying the address to start
loading the program words and then a 24-bit word for each program word to be loaded. The program words will be stored
Mode C in contiguous PRAM memory locations starting at the specified starting address. After reading the program words,
program execution starts from the same address where loading started. The Host Interface bootstrap load program may be
stopped by setting the Host Flag 0 (HF0). This will start execution of the loaded program from the specified starting
address.
As in Mode C, but HDI08 is set for interfacing to Motorola HC11 microcontroller in non-multiplexed mode
Mode D
As in Mode C, but HDI08 is set for interfacing to Intel 8051 multiplexed bus
Mode E
6-6
Table 6-3 DSP56367 Mode Descriptions
DSP56367
2
C slave mode with HCKFR set to 1 and the 100ns filter enabled.
2
C slave mode with HCKFR set to 0.
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