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10.3.1.9
TCCR Transmit Frame Sync Signal Direction (TFSD) - Bit 22
TFSD controls the direction of the FST pin. When TFSD is cleared, FST is an input; when
TFSD is set, FST is an output. See Table 10-2.
10.3.1.10
TCCR Transmit High Frequency Clock Direction (THCKD) - Bit 23
THCKD controls the direction of the HCKT pin. When THCKD is cleared, HCKT is an input;
when THCKD is set, HCKT is an output. See Table 10-2.
10.3.2
ESAI TRANSMIT CONTROL REGISTER (TCR)
The read/write Transmit Control Register (TCR) controls the ESAI transmitter section.
Interrupt enable bits for the transmitter section are provided in this control register. Operating
modes are also selected in this register. See Figure 10-5.
11
X:$FFFFB5
TSWS1 TSWS0 TMOD1 TMOD0 TWA TSHFD
23
TLIE
Hardware and software reset clear all the bits in the TCR register.
The TCR bits are described in the following paragraphs.
10.3.2.1
TCR ESAI Transmit 0 Enable (TE0) - Bit 0
TE0 enables the transfer of data from TX0 to the transmit shift register #0. When TE0 is set
and a frame sync is detected, the transmit #0 portion of the ESAI is enabled for that frame.
When TE0 is cleared, the transmitter #0 is disabled after completing transmission of data
currently in the ESAI transmit shift register. The SDO0 output is tri-stated, and any data
present in TX0 is not transmitted (i.e., data can be written to TX0 with TE0 cleared; but data is
not transferred to the transmit shift register #0).
The normal mode transmit enable sequence is to write data to one or more transmit data
registers before setting TEx. The normal transmit disable sequence is to clear TEx, TIE and
TEIE after TDE equals one.
MOTOROLA
10
9
8
7
22
21
20
19
TIE
TEDIE
TEIE
TPR
Reserved bit - read as zero; should be written with zero for future compatibility.
Figure 10-5 TCR Register
DSP56367
Enhanced Serial Audio Interface (ESAI)
ESAI Programming Model
6
5
4
3
TE5
TE4
TE3
18
17
16
15
PADC
TFSR
TFSL TSWS4 TSWS3 TSWS2
2
1
0
TE2
TE1
TE0
14
13
12
10-15
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