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10.3.6.4
SAISR Reserved Bits - Bits 3-5, 11-12, 18-23
These bits are reserved for future use. They read as zero.
10.3.6.5
SAISR Receive Frame Sync Flag (RFS) - Bit 6
When set, RFS indicates that a receive frame sync occurred during reception of the words in
the receiver data registers. This indicates that the data words are from the first slot in the
frame. When RFS is clear and a word is received, it indicates (only in the network mode) that
the frame sync did not occur during reception of that word. RFS is cleared by hardware,
software, ESAI individual, or STOP reset. RFS is valid only if at least one of the receivers is
enabled (REx=1).
Note:
In normal mode, RFS always reads as a one when reading data because there is
only one time slot per frame – the "frame sync" time slot.
10.3.6.6
SAISR Receiver Overrun Error Flag (ROE) - Bit 7
The ROE flag is set when the serial receive shift register of an enabled receiver is full and
ready to transfer to its receiver data register (RXx) and the register is already full (RDF=1). If
REIE is set, an ESAI receive data with exception (overrun error) interrupt request is issued
when ROE is set. Hardware, software, ESAI individual, and STOP reset clear ROE. ROE is
also cleared by reading the SAISR with ROE set, followed by reading all the enabled receive
data registers.
10.3.6.7
SAISR Receive Data Register Full (RDF) - Bit 8
RDF is set when the contents of the receive shift register of an enabled receiver is transferred
to the respective receive data register. RDF is cleared when the DSP reads the receive data
register of all enabled receivers or cleared by hardware, software, ESAI individual, or STOP
reset. If RIE is set, an ESAI receive data interrupt request is issued when RDF is set.
10.3.6.8
SAISR Receive Even-Data Register Full (REDF) - Bit 9
When set, REDF indicates that the received data in the receive data registers of the enabled
receivers have arrived during an even time slot when operating in the network mode. Even
time slots are all even-numbered slots (0, 2, 4, 6, etc.). Time slots are numbered from zero to
N-1, where N is the number of time slots in the frame. The zero time slot is considered even.
REDF is set when the contents of the receive shift registers are transferred to the receive data
registers. REDF is cleared when the DSP reads all the enabled receive data registers or cleared
by hardware, software, ESAI individual, or STOP resets. If REDIE is set, an ESAI receive
even slot data interrupt request is issued when REDF is set.
10.3.6.9
SAISR Receive Odd-Data Register Full (RODF) - Bit 10
When set, RODF indicates that the received data in the receive data registers of the enabled
receivers have arrived during an odd time slot when operating in the network mode. Odd time
slots are all odd-numbered slots (1, 3, 5, etc.). Time slots are numbered from zero to N-1,
where N is the number of time slots in the frame. RODF is set when the contents of the receive
MOTOROLA
Enhanced Serial Audio Interface (ESAI)
DSP56367
ESAI Programming Model
10-39
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