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8.6.3.5
ISR Host Flag 3 (HF3) Bit 4
The HF3 bit in the ISR indicates the state of host flag 3 in the HCR on the DSP side. HF3 can
be changed only by the DSP (see Section 8.5.3.4).
8.6.3.6
ISR Reserved Bits 5-6
These bits are reserved. They read as zero and should be written with zero for future
compatibility.
8.6.3.7
ISR Host Request (HREQ) Bit 7
The HREQ bit indicates the status of the external host request output signal (HOREQ) if
HDRQ is cleared. If HDRQ is set, it indicates the status of the external transmit and receive
request output signals (HTRQ and HRRQ).
HREQ
Status [HDRQ=0]
0
HOREQ deasserted; no host processor interrupt is requested HTRQ and HRRQ deasserted; no host processor interrupts are
1
HOREQ asserted; a host processor interrupt is requested
The HREQ bit may be set from either or both of two conditions – either the receive byte
registers are full or the transmit byte registers are empty. These conditions are indicated by the
ISR RXDF and TXDE status bits, respectively. If the interrupt source has been enabled by the
associated request enable bit in the ICR, HREQ is set if one or more of the two enabled
interrupt sources is set.
8.6.4
INTERRUPT VECTOR REGISTER (IVR)
The IVR is an 8-bit read/write register which typically contains the interrupt vector number
used with MC68000 Family processor vectored interrupts. Only the host processor can read
and write this register. The contents of IVR are placed on the host data bus (H0–H7) when
both the HOREQ and HACK signals are asserted. The contents of this register are initialized
to $0F by hardware or software reset, which corresponds to the uninitialized interrupt vector
in the MC68000 Family.
Figure 8-15 Interrupt Vector Register (IVR)
7
6
IV7
IV6
MOTOROLA
Table 8-14 Host Request Status (HREQ)
5
4
IV5
IV4
DSP56367
HDI08 – External Host Programmer's Model
Status [HDRQ=1]
requested
HTRQ and/or HRRQ asserted; host processor interrupts are
requested
3
2
IV3
IV2
Host Interface (HDI08)
1
0
IV1
IV0
8-27
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