Servicing Interrupts - Motorola DSP56367 User Manual

5. If HREQ=1, the HOREQ/HTRQ/HRRQ signal has been asserted, and the DSP is
requesting the attention of the host processor. One of the previous four conditions
exists.
After the appropriate data transfer has been made, the corresponding status bit is updated to
reflect the transfer.
If the host processor has issued a command to the DSP by writing the CVR and setting the HC
bit, it can read the HC bit in the CVR to determine when the command has been accepted by
the interrupt controller in the DSP core. When the command has been accepted for execution,
the HC bit is cleared by the interrupt controller in the DSP core.
7
$2
HREQ 0
Host Request
ASSERTED
7
$0
INIT 0 HLEND
Figure 8-16 HDI08 Host Request Structure
8.7.3

SERVICING INTERRUPTS

If either the HOREQ/HTRQ or the HRRQ signal or both are connected to the host processor
interrupt inputs, the HDI08 can request service from the host processor by asserting one of
these signals. The HOREQ/HTRQ and/or the HRRQ signal is asserted when TXDE=1 and/or
RXDF=1 and the corresponding enable bit (TREQ or RREQ, respectively) is set. This is
depicted in Figure 8-16.
HOREQ/HTRQ and HRRQ are normally connected to the host processor maskable interrupt
inputs. The host processor acknowledges host interrupts by executing an interrupt service
routine. The host processor can test RXDF and TXDE to determine the interrupt source. The
host processor interrupt service routine must read or write the appropriate HDI08 data register
to clear the interrupt. HOREQ/HTRQ and/or HRRQ is deasserted under the following
conditions:
MOTOROLA
0 HF3 HF2 TRDY
HF1 HF0 HDRQ
DSP56367
Servicing The Host Interface
STATUS
0
TXDE RXDF ISR
0
TREQ RREQ ICR
ENABLE
Host Interface (HDI08)
HRRQ
HOREQ
HTRQ
8-31