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Enhanced Serial Audio Interface (ESAI)
ESAI Programming Model
Table 10-3 Transmitter High Frequency Clock Divider
10.3.1.5
TCCR Transmit Clock Polarity (TCKP) - Bit 18
The Transmitter Clock Polarity (TCKP) bit controls on which bit clock edge data and frame
sync are clocked out and latched in. If TCKP is cleared the data and the frame sync are
clocked out on the rising edge of the transmit bit clock and latched in on the falling edge of the
transmit bit clock. If TCKP is set the falling edge of the transmit clock is used to clock the
data out and frame sync and the rising edge of the transmit clock is used to latch the data and
frame sync in.
10.3.1.6
TCCR Transmit Frame Sync Polarity (TFSP) - Bit 19
The Transmitter Frame Sync Polarity (TFSP) bit determines the polarity of the transmit frame
sync signal. When TFSP is cleared, the frame sync signal polarity is positive (i.e the frame
start is indicated by a high level on the frame sync pin). When TFSP is set, the frame sync
signal polarity is negative (i.e the frame start is indicated by a low level on the frame sync
pin).
10.3.1.7
TCCR Transmit High Frequency Clock Polarity (THCKP) - Bit 20
The Transmitter High Frequency Clock Polarity (THCKP) bit controls on which bit clock
edge data and frame sync are clocked out and latched in. If THCKP is cleared the data and the
frame sync are clocked out on the rising edge of the transmit bit clock and latched in on the
falling edge of the transmit bit clock. If THCKP is set the falling edge of the transmit clock is
used to clock the data out and frame sync and the rising edge of the transmit clock is used to
latch the data and frame sync in.
10.3.1.8
TCCR Transmit Clock Source Direction (TCKD) - Bit 21
The Transmitter Clock Source Direction (TCKD) bit selects the source of the clock signal
used to clock the transmit shift registers in the asynchronous mode (SYN=0) and the transmit
shift registers and the receive shift registers in the synchronous mode (SYN=1). When TCKD
is set, the internal clock source becomes the bit clock for the transmit shift registers and word
length divider and is the output on the SCKT pin. When TCKD is cleared, the clock source is
external; the internal clock generator is disconnected from the SCKT pin, and an external
clock source may drive this pin. See Table 10-2.
10-14
TFP3-TFP0
$0
$1
$2
$3
...
$F
DSP56367
Divide Ratio
1
2
3
4
...
16
MOTOROLA
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