Hcsr Bus-Error Interrupt Enable (Hbie)—Bit 10 - Motorola DSP56367 User Manual

Serial Host Interface
Serial Host Interface Programming Model
Note: Programmers should take care to ensure that all DMA channel service to HTX is
disabled before setting HIDLE.
9.5.6.9 HCSR Bus-Error Interrupt Enable (HBIE)—Bit 10
The read/write control bit HBIE is used to enable the SHI bus-error interrupt. If HBIE is
cleared, bus-error interrupts are disabled, and the HBER status bit must be polled to determine
if an SHI bus error occurred. If both HBIE and HBER are set, the SHI requests an SHI
bus-error interrupt service from the interrupt controller. HBIE is cleared by hardware reset
and software reset.
Note: Clearing HBIE masks a pending bus-error interrupt only after a one instruction
cycle delay. If HBIE is cleared in a long interrupt service routine, it is
recommended that at least one other instruction separate the instruction that clears
HBIE and the RTI instruction at the end of the interrupt service routine.
9.5.6.10 HCSR Transmit-Interrupt Enable (HTIE)—Bit 11
The read/write control bit HTIE is used to enable the SHI transmit data interrupts. If HTIE is
cleared, transmit interrupts are disabled, and the HTDE status bit must be polled to determine
if HTX is empty. If both HTIE and HTDE are set and HTUE is cleared, the SHI requests an
SHI transmit-data interrupt service from the interrupt controller. If both HTIE and HTUE are
set, the SHI requests an SHI transmit-underrun-error interrupt service from the interrupt
controller. HTIE is cleared by hardware reset and software reset.
Note: Clearing HTIE masks a pending transmit interrupt only after a one instruction
cycle delay. If HTIE is cleared in a long interrupt service routine, it is
recommended that at least one other instruction separate the instruction that clears
HTIE and the RTI instruction at the end of the interrupt service routine.
9.5.6.11 HCSR Receive Interrupt Enable (HRIE[1:0])—Bits 13–12
The read/write control bits HRIE[1:0] are used to enable the SHI receive-data interrupts. If
HRIE[1:0] are cleared, receive interrupts are disabled, and the HRNE and HRFF (bits 17 and
19, see below) status bits must be polled to determine if there is data in the receive FIFO. If
HRIE[1:0] are not cleared, receive interrupts are generated according to Table 9-6. HRIE[1:0]
are cleared by hardware and software reset.
Table 9-6 HCSR Receive Interrupt Enable Bits
HRIE[1:0]
00
01
10
9-16
Interrupt
Disabled
Receive FIFO not empty
Receive Overrun Error
Reserved
DSP56367
Condition
Not applicable
HRNE = 1 and HROE = 0
HROE = 1
Not applicable
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