Table 4-3 Interrupt Priority Level Bits - Motorola DSP56309 User Manual

Core Configuration
Interrupt Sources and Priorities
4.4.2 Interrupt Priority Levels
The DSP56309 has a four-level interrupt priority structure. Each interrupt has two
interrupt priority level bits (IPL[1:0]) that determine its interrupt priority level. Level 0 is
the lowest priority; Level 3 is the highest-level priority and is non-maskable. Table 4-3
defines the IPL bits.
xxL1
4-12

Table 4-3 Interrupt Priority Level Bits

IPL bits
Interrupts
Enabled
xxL0
0 0 No
0 1 Yes
1 0 Yes
1 1 Yes
DSP56309UM/D
Interrupt
Interrupts
Priority
Masked
Level
Ñ 0
0 1
0, 1 2
0, 1, 2 3
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