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MB86R02 'Jade-D' Hardware Manual V1.64
*1: The board must be designed to ensure that the high-impedance bus does not leave the logic state of the
final driven bit for this time period. Therefore, coupling must be minimized while meeting the maximum
capacitive load listed.
34.5.14.2
MediaLB AC Spec Type B
Ground = 0V, Load capacitance = 40pF, MediaLB speed = 1024Fs, and Fs = 48kHz.
All timing parameters are specified from the valid voltage threshold as listed below; unless
otherwise noted.
9.1.1.1.2.
Clock
Table 34-39 AC Timing of Clock Signal
Signal
MLBCLK
*1: The controller can shut off MLBCLK to place MediaLB in a low-power state.
*2: Pulse width variation is measured at 1.25V by triggering on one edge of MLBCLK and measuring the spread on
the other edge, measured in ns peak-to-peak (pp).
9.1.1.1.3.
Input Signal
Table 34-40 AC Timing of Input Signal
Signal Name
MLBSIG, MLBDAT
input
9.1.1.1.4.
Output signal
Table 34-41 AC Timing of Output Signal
Signal Name
MLBSIG, MLBDAT
Output
34-42
Symbo
Description
l
MLBCLK operating frequency
f
mck
(*1)
t
MLBCLK rising time
mckr
t
MLBCLK falling time
mckf
t
MLBCLK cycle time
mckc
t
MLBCLK low time
mckl
t
MLBCLK high time
mckh
t
MLBCLK pulse width variation
mpwv
Symbo
Description
l
MLBSIG and MLBDAT input
t
dsmcf
valid to MLBCLK falling
MLBSIG and MLBDAT input
t
dhmcf
hold from MLBCLK low
Symbo
Description
l
MLBSIG and MLBDAT output
t
high impedance from MLBCLK
mcfdz
low
t
Bus hold time
mdzh
Value
Min.
Typ.
Max.
45.056
–
–
–
49.152
–
–
–
49.2544
–
–
1
–
–
1
–
20.3
–
6.8
7.8
–
9.7
10.4
–
–
–
0.5
Value
Unit
Min.
Typ.
Max.
1
–
–
0
–
–
Value
Unit
Min.
Typ.
Max.
t
0
–
mckl
2
–
–
Uni
Comment
t
1024xFs at 44.0kHz
MHz
1024xFs at 48.0kHz
1024xFs at 48.1kHz
ns V
to V
IL
IH
ns V
to V
IH
IL
ns
ns
ns
ns
(*2)
pp
Comment
ns
ns
Comment
ns
ns (*1)
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