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MB86R02 'Jade-D' Hardware Manual V1.64
It requires at least 100 clocks (input clock to CLK pin) for the reset signal "L" applied to the XRST
pin to be transmitted to all internal circuits.
34.3.2
Power On Reset
VDDI (internal)
VDDE (external)
DDRVDE (DRAM)
Input clock immediately
after power-on
Internal
clock generated by
ECLK or XTAL
Input "L" when power-on
XTRST
Input "L" when power-on
XRST
output "L" when power-on
XSRST
Figure 34-3 Power On Sequence
Input XTRST and XRST pins to Low when power-on.
Keep XTRST and XRST pins High after setting to Low level for 8µs or more.
Access the other registers or memory controller after PLL Lockup Time.
34-4
Note: Clock is just an image, not the actual one.
8 µs or more
PLL Lockup Time
Input when XRST is "H" after "L"
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