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MB86R02 'Jade-D' Hardware Manual V1.64
RGBHC(RGB input Hsync Cycle)
Register address
Bit number
Bit field name
R/W
Initial value
Bit13-0
RGBHEN(RGB input Horizontal Enable area)
Register address
Bit number
Bit field name
R/W
Initial value
It is a parameter for determining effective pixel data.
Bit12-0
Bit27-16
Note: The maximum horizontal enable area size(RGBHEN) which can be captured is 840 pixels.
This is the restriction by line buffer size in a video capture module.
RGBVEN(RGB input Vertical Enable area)
Register address
Bit number
Bit field name
R/W
Initial value
It is a parameter for determining effective pixel data.
Bit12-0
Bit24-16
CaptureBaseAddress + 80h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Reserved
RGBHC
This register sets number of HSYNC cycles of the RGB input. . It is used when it is made a setup
which samples VSYNC. The setting value +1 is a level cycle.
CaptureBaseAddress + 84h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Reserved
RX
X
RGBHEN(RGB input Horizontal Enable area Size)
Effective pixel data size is set up per pixel. Specify the number of horizontal pixels in 2-pixel units
RGBHST(RGB input Horizontal Enable area Start position)
The start position of effective pixel data is set up. The setting value -4 is a start position.
CaptureBaseAddress + 88h
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Reserv
Reserved
ed
RX
R/W
X
X
RGBVEN(RGB input Vertical Enable area Size)
Set effective line size
RGBVST(RGB input Vertical Enable area Start position)
The start position of effective line is set up. The setting value -1 is a start position.
RX
X
RGBHST
Reserved
R/W
RX
X
X
RGBVST
Reserved
R/W
RX
X
X
9
8
7
6
5
4
3
2
1
RGBHC
R/W
X
9
8
7
6
5
4
3
2
1
RGBHEN
R/W
X
9
8
7
6
5
4
3
2
1
RGBVEN
R/W
X
18-131
0
0
0
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