Register Summary - Fujitsu MB86R02 Jade-D Hardware Manual

MB86R02 'Jade-D' Hardware Manual V1.64

17.3.3 Register Summary

Address
Base address + 0
H
Base address + 4
H
Base address + 8
H
Base address + C
H
Base address + 10
H
Base address + 14
H
Base address + 18
H
Base address + 1C
H
Base address + 20
H
Base address + 24
H
Base address + 28
H
Base address + 2C
H
Base address + 34
H
Base address + 38
H
Base address + 3C
H
Base address + 40
H
Base address + 44
H
Base address + 48
H
Base address + 4C
H
Base address + 50
H
Base address + 54
H
Base address + 58
H
Base address + 5C
H
Base address + 60
H
Base address + 64
H
Base address + 68
H
Base address + 6C
H
Base address + 74
H
Base address + 78
H
Base address + 7C
H
Base address + 100
H
Base address + 104
H
Base address + 10C
H
Register Name
CH0CFG Channel 0 Config
T0CFG0 Channel 0 TX APIX configuration byte 1-4
T0CFG1 Channel 0 TX APIX configuration byte 5-8
T0CFG2 Channel 0 TX APIX configuration byte 9-11
T0CFG3 Channel 0 TX APIX SHELL configuration byte1-4
T0CFG4 Channel 0 TX APIX configuration
T0CTRL Channel 0 TX control
T0STS0 Channel 0 TX status register 0
T0STS1 Channel 0 TX status register 1
R0CFG0 Channel 0 RX APIX configuration byte 1-4
R0CFG1 Channel 0 RX APIX configuration byte 5-7
R0CFG2 Channel 0 RX APIX SHELL configuration byte 1-4
R0CTRL Channel 0 RX control
R0STS0 Channel 0 RX status register 0
R0STS1 Channel 0 RX status register 1
CH1CFG Channel 1 Config
T1CFG0 Channel 1 TX APIX configuration byte 1-4
T1CFG1 Channel 1 TX APIX configuration byte 5-8
T1CFG2 Channel 1 TX APIX configuration byte 9-11
T1CFG3 Channel 1 TX APIX SHELL configuration byte1-4
T1CFG4 Channel 1 TX APIX configuration channel 1
T1CTRL Channel 1 TX control
T1STS0 Channel 1 TX status register 0
T1STS1 Channel 1 TX status register 1
R1CFG0 Channel 1 RX APIX configuration byte 1-4
R1CFG1 Channel 1 RX APIX configuration byte 5-7
R1CFG2 Channel 1 RX APIX SHELL configuration byte 1-4
R1CTRL Channel 1 RX 0 control
R1STS0 Channel 1 RX status register 0
R1STS1 Channel 1 RX status register 1
COMPHYCFG0 Common APIX configuration 0
COMPHYCFG1 Common APIX configuration 1
APPLLCFG PLL/Oscillator configuration
Description
17-5