Table of Contents
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11/2/95
TABLE OF CONTENTS (Continued)
Paragraph
Number
3.4
CPU Space Cycles........................................................................................... 3-21
3.4.1
Breakpoint Acknowledge Cycle................................................................. 3-22
3.4.2
LPSTOP Broadcast Cycle........................................................................... 3-23
3.4.3
Module Base Address Register Access.................................................... 3-27
3.4.4
Interrupt Acknowledge Bus Cycles............................................................ 3-27
3.4.4.1
Interrupt Acknowledge Cycle-Terminated Normally........................ 3-27
3.4.4.2
Autovector Interrupt Acknowledge Cycle ............................................. 3-29
3.4.4.3
Spurious Interrupt Cycle.......................................................................... 3-30
3.5
Bus Exception Control Cycles........................................................................ 3-32
3.5.1
Bus Errors....................................................................................................... 3-34
3.5.2
Retry Operation ............................................................................................. 3-36
3.5.3
Halt Operation ............................................................................................... 3-38
3.5.4
Double Bus Fault .......................................................................................... 3-39
3.6
Bus Arbitration................................................................................................... 3-40
3.6.1
Bus Request................................................................................................... 3-43
3.6.2
Bus Grant........................................................................................................ 3-43
3.6.3
Bus Grant Acknowledge.............................................................................. 3-43
3.6.4
Bus Arbitration Control................................................................................. 3-44
3.6.5
Show Cycles.................................................................................................. 3-44
3.7
Reset Operation ................................................................................................ 3-46
4.1
Module Overview.............................................................................................. 4-1
4.2
Module Operation............................................................................................. 4-2
4.2.1
Module Base Address Register Operation............................................... 4-2
4.2.2
System Configuration and Protection Operation.................................... 4-3
4.2.2.1
System Configuration .............................................................................. 4-5
4.2.2.2
Internal Bus Monitor ................................................................................. 4-6
4.2.2.3
Double Bus Fault Monitor........................................................................ 4-6
4.2.2.4
Spurious Interrupt Monitor ...................................................................... 4-6
4.2.2.5
Software Watchdog.................................................................................. 4-6
4.2.2.6
Periodic Interrupt Timer ........................................................................... 4-7
4.2.2.6.1
Periodic Timer Period Calculation..................................................... 4-8
4.2.2.6.2
Using the Periodic Timer as a Real-Time Clock ............................. 4-9
4.2.2.7
Simultaneous Interrupts by Sources in the SIM40............................. 4-9
4.2.3
Clock Synthesizer Operation...................................................................... 4-9
4.2.3.1
Phase Comparator and Filter ................................................................. 4-11
4.2.3.2
Frequency Divider .................................................................................... 4-12
4.2.3.3
Clock Control............................................................................................. 4-13
4.2.4
Chip Select Operation ................................................................................. 4-13
4.2.4.1
Programmable Features.......................................................................... 4-14
vi
Freescale Semiconductor, Inc.
SECTION 1: OVERVIEW
Title
Section 4
MC68340 USER'S MANUAL
For More Information On This Product,
Go to: www.freescale.com
UM Rev.1.0
P a g e
Number
MOTOROLA
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